pca24s08a NXP Semiconductors, pca24s08a Datasheet

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pca24s08a

Manufacturer Part Number
pca24s08a
Description
1024 ? 8-bit Cmos Eeprom With Access Protection
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
The PCA24S08A provides 8192 bits of serial Electrically Erasable and Programmable
Read-Only Memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are
received and transmitted via the serial I
Access permissions limiting reads or writes are set via the I
memory from improper access.
The PCA24S08A is intended to be pin compatible with standard 24C08 serial EEPROM
devices except for pins 1, 2, and 3, which are address pins in the standard part. Other
exceptions to the PCA24S08A serial EEPROM data sheet are noted in
All bits are sent to or read from the device, most significant bit first, in a manner consistent
with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed
with the MSB on the left and the LSB on the right.
The EEPROM memory is broken up into 8 blocks of 1 kbit (128 bytes) each. Within each
block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In
addition to these 8 kbits, there are two more 128-bit pages that are used to store the
access protection and ID information. There are a total of 8448 bits of EEPROM memory
available in the PCA24S08A.
Access protection (both read and write) is organized on a block basis for block 1 through
block 7 and on a page and a block basis for block 0. Protection information for these
blocks and pages is stored in one of the additional pages of EEPROM memory that is
addressed separately from the main data storage array.
The ID value is located in the ID page of the EEPROM, the second of the additional
16 byte pages.
Writes from the serial interface may include from one byte to 16 bytes at a time,
depending on the protocol followed by the bus master. All page accesses must be
properly aligned to the internal EEPROM page.
The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year
data retention. Writes to the EEPROM take less than 5 ms to complete.
After manufacturing, all EEPROM bits will be set to a value of ‘1’.
PCA24S08A
1024 × 8-bit CMOS EEPROM with access protection
Rev. 01 — 19 January 2010
2
C-bus.
SeeSection 6.4
2
C-bus to isolate blocks of
Product data sheet
Section
for more details.
6.6.

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pca24s08a Summary of contents

Page 1

... Access permissions limiting reads or writes are set via the I memory from improper access. The PCA24S08A is intended to be pin compatible with standard 24C08 serial EEPROM devices except for pins 1, 2, and 3, which are address pins in the standard part. Other exceptions to the PCA24S08A serial EEPROM data sheet are noted in All bits are sent to or read from the device, most significant bit first manner consistent with the 24C08 serial EEPROM ...

Page 2

... CMOS EEPROM with access protection Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm Rev. 01 — 19 January 2010 PCA24S08A Version SOT96-1 SOT505-1 © NXP B.V. 2010. All rights reserved ...

Page 3

... SDA SS 002aae784 Rev. 01 — 19 January 2010 PCA24S08A DIVIDER SEQUENCER (÷ 128) EE CONTROL TIMER (÷ 16) OSCILLATOR 002aae786 n. n.c. WP PCA24S08ADP PROT 3 6 SCL SDA SS 002aae785 Fig 3. Pin configuration for TSSOP8 © NXP B.V. 2010. All rights reserved. WP PROT ...

Page 4

... PCA24S08A responds with an acknowledge and awaits the next 8 bits of data, again responding with an acknowledge. Word address is automatically incremented. ...

Page 5

... Product data sheet 1024 × 8-bit CMOS EEPROM with access protection BLOCK BLOCK R/W B0 fixed block number Rev. 01 — 19 January 2010 PCA24S08A BYTE PAGE BYTE BYTE PAGE BYTE 15 ...

Page 6

... A[3:0] is the byte address within the page. Bits denoted as ‘X’ are ignored by the device. 6.2.2 Page write The PCA24S08A is capable of a 16-byte page write operation initiated in the same manner as the byte write operation. The master can transit 16 data bytes within one transmission. After receipt of each byte, the PCA24S08A will respond with an acknowledge ...

Page 7

... EEPROM slave transmitter (cont ReSTART condition Fig 8. Master reads PCA24S08A slave after setting word address (write word address: read data); sequential read PCA24S08A_1 Product data sheet 1024 × 8-bit CMOS EEPROM with access protection word address acknowledge ...

Page 8

... PCA24S08A memory. See “Access Protection Page (APP)” 6.4.1 RFID access fields (RF) Even though the PCA24S08A does not have the RFID capability, RFID access fields (RF) can be stored in order to keep existing software compatibility. The fields are stored in the EEPROM and organized as shown in Table 3 ...

Page 9

... EEPROM block 0 to block 7, controlled by PB0 to PB7. • The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled by PBAP. PCA24S08A_1 Product data sheet 1024 × 8-bit CMOS EEPROM with access protection Rev. 01 — 19 January 2010 PCA24S08A © NXP B.V. 2010. All rights reserved ...

Page 10

... NXP Semiconductors 6.4.2.1 Block 0 write protection bits The PCA24S08A provides a mechanism to divide block 0 into eight 128-bit (16-byte) pages that can be individually protected against writes. These eight write protection (WPN) bits are stored within a byte of the access protection page and are organized such that the LSB protects the first 128 bits, and so on ...

Page 11

... As an example, the bit encoding for a single byte read and write command are shown in Figure 11. The PCA24S08A will acknowledge all device addresses of B8h or B9h. If the most significant three its of the word address are not all 0 (indicating an address outside the Access protection and ID pages), the chip will NACK the access. ...

Page 12

... Rev. 01 — 19 January 2010 PCA24S08A 002aae843 P0 is used to distinguish between the APP and RFID pages APP pages 1 = RFID pages 002aae844 Table 5 “APP memory © NXP B.V. 2010. All rights reserved. ...

Page 13

... When HIGH, activity on the serial bus is permitted and sticky bits can be set to their values. 6.6 Serial EEPROM exceptions In general, the two-wire serial interface on the PCA24S08A functions identically to the 24C08. The following exceptions exist, as noted elsewhere in this document. • ...

Page 14

... DD SS PROT, SDA, SCL pins pin 5 2 SCL, PROT, WP not tested SDA not tested Rev. 01 — 19 January 2010 PCA24S08A Min Max Unit - 4.6 V −0 +0 −55 °C +125 −40 °C +85 Min Typ Max Unit 2 ...

Page 15

... CMOS EEPROM with access protection = 2 3 Conditions Standard-mode Min 0 4.7 4.0 4.7 4.0 0 [1] - [2] LOW level - [2] HIGH level - 250 4.7 4 HD;DAT HIGH SU;DAT Rev. 01 — 19 January 2010 PCA24S08A 2 Fast-mode I C-bus 2 I C-bus Max Min Max 100 0 400 - 600 - 600 600 - 600 1500 - 600 ...

Page 16

... Parameter data retention at operating temperature endurance per byte PCA24S08A_1 Product data sheet 1024 × 8-bit CMOS EEPROM with access protection EEPROM memory specifications Specification 10 years (minimum) 100,000 cycles (minimum) Rev. 01 — 19 January 2010 PCA24S08A © NXP B.V. 2010. All rights reserved ...

Page 17

... 0.49 0.25 5.0 4.0 6.2 1.27 0.36 0.19 4.8 3.8 5.8 0.019 0.0100 0.20 0.16 0.244 0.05 0.041 0.014 0.0075 0.19 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 01 — 19 January 2010 PCA24S08A θ detail 1.0 0.7 1.05 0.25 0.25 0.1 0.4 0.6 0.039 0.028 0.028 0.01 0.01 0.004 0.016 ...

Page 18

... CMOS EEPROM with access protection 2.5 scale (1) ( 0.45 0.28 3.1 3.1 5.1 0.65 0.94 0.25 0.15 2.9 2.9 4.7 REFERENCES JEDEC JEITA Rev. 01 — 19 January 2010 PCA24S08A θ detail θ ( 0.7 0.70 6° 0.1 0.1 0.1 0.4 0.35 0° EUROPEAN ISSUE DATE PROJECTION 99-04-09 03-02-18 © ...

Page 19

... Solder bath specifications, including temperature and impurities PCA24S08A_1 Product data sheet 1024 × 8-bit CMOS EEPROM with access protection Rev. 01 — 19 January 2010 PCA24S08A © NXP B.V. 2010. All rights reserved ...

Page 20

... Lead-free process (from J-STD-020C) Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 15. Rev. 01 — 19 January 2010 PCA24S08A Figure 15) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2010. All rights reserved. ...

Page 21

... Human Body Model Inter-Integrated Circuit bus Input/Output Least Significant Bit Machine Model Most Significant Bit Not Acknowledge Protection Bit Radio Frequency Radio Frequency Identification Sticky Bit Rev. 01 — 19 January 2010 PCA24S08A peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...

Page 22

... Table 13. Revision history Document ID Release date PCA24S08A_1 20100119 PCA24S08A_1 Product data sheet 1024 × 8-bit CMOS EEPROM with access protection Data sheet status Change notice Product data sheet - Rev. 01 — 19 January 2010 PCA24S08A Supersedes - © NXP B.V. 2010. All rights reserved ...

Page 23

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 19 January 2010 PCA24S08A © NXP B.V. 2010. All rights reserved ...

Page 24

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: PCA24S08A_1 All rights reserved. Date of release: 19 January 2010 ...

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