pca9671 NXP Semiconductors, pca9671 Datasheet

no-image

pca9671

Manufacturer Part Number
pca9671
Description
Remote 16-bit I/o Expander For Fm+ I2c-bus With Reset
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
pca9671D
Manufacturer:
NXP
Quantity:
7 609
Part Number:
pca9671D
Manufacturer:
NXP
Quantity:
7 363
Part Number:
pca9671PW
Manufacturer:
NXP
Quantity:
2 031
Part Number:
pca9671PWЈ¬118
Manufacturer:
NXP
Quantity:
2 067
1. General description
2. Features
The PCA9671 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I
(Fm+) family.
The PCA9671 is a drop in upgrade for the PCF8575 providing higher I
(1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher
I
the need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) that
supports having all 25 mA LEDs on at the same time and more device addresses (64
versus 8) to allow many more devices on the bus without address conflicts.
The difference between the PCA9671 and the PCF8575 is that the interrupt output on the
PCF8575 is replaced by a RESET input on the PCA9671.
The device consists of a 16-bit quasi-bidirectional port and an I
PCA9671 has a low current consumption and includes latched outputs with 25 mA high
current drive capability for directly driving LEDs. The internal Power-On Reset (POR),
hardware reset pin (RESET) or software reset sequence initializes the I/Os as inputs.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without
PCA9671
Remote 16-bit I/O expander for Fm+ I
Rev. 01 — 20 December 2006
1 MHz I
Compliant with the I
SDA with 30 mA sink capability for 4000 pF buses
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
16-bit remote I/O pins that default to inputs at power-up
Latched outputs with 25 mA sink capability for directly driving LEDs
Total package sink capability of 400 mA
Active LOW reset input
64 programmable slave addresses using 3 address pins
Readable device ID (manufacturer, device type, and revision)
Low standby current
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
Packages offered: SO24, SSOP24, QSOP24, TSSOP24, HVQFN24, DHVQFN24
40 C to +85 C operation
2
C-bus interface
2
C-bus Fast-mode and Standard-mode
2
C-bus) and is a part of the Fast-mode Plus
2
C-bus with reset
2
C-bus interface. The
Product data sheet
2
C-bus speeds

Related parts for pca9671

pca9671 Summary of contents

Page 1

... LEDs on at the same time and more device addresses (64 versus 8) to allow many more devices on the bus without address conflicts. The difference between the PCA9671 and the PCF8575 is that the interrupt output on the PCF8575 is replaced by a RESET input on the PCA9671. ...

Page 2

... Name PCA9671D PCA9671D SO24 PCA9671DB PCA9671DB SSOP24 PCA9671DK PCA9671 SSOP24 PCA9671PW PCA9671PW TSSOP24 PCA9671BQ 9671 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad PCA9671BS 9671 HVQFN24 [1] Also known as QSOP24. PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm+ I Description plastic small outline package ...

Page 3

... NXP Semiconductors 5. Block diagram AD0 AD1 AD2 SCL SDA RESET Fig 1. Block diagram of PCA9671 data from Shift Register data to Shift Register Fig 2. Simplified schematic diagram of P00 to P17 PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm+ I PCA9671 2 INPUT I C-BUS ...

Page 4

... P11 P10 SS 002aac270 (QSOP24) Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset 1 RESET AD1 2 AD2 3 4 P00 5 P01 P02 6 PCA9671PW P03 7 8 P04 P05 9 P06 10 11 P07 002aac246 Fig 4. Pin configuration for TSSOP24 RESET 1 AD1 2 3 AD2 4 P00 ...

Page 5

... I quasi-bidirectional I quasi-bidirectional I/O 07 [1] 9 supply ground 10 quasi-bidirectional I quasi-bidirectional I quasi-bidirectional I quasi-bidirectional I quasi-bidirectional I quasi-bidirectional I quasi-bidirectional I quasi-bidirectional I/O 17 PCA9671 2 C-bus with reset 23 SDA 22 SCL 21 AD0 20 P17 19 P16 18 P15 17 P14 16 P13 15 P12 14 P11 002aac271 © NXP B.V. 2006. All rights reserved. ...

Page 6

... AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in Table 3 “PCA9671 address Remark: The General Call address (0000 0000) and the Device ID address (1111 100X) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA9671 not to acknowledge. Remark: Reserved I with: • ...

Page 7

... PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm+ I PCA9671 address map AD1 AD0 SCL SCL SDA SDA SCL ...

Page 8

... SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA SCL SCL SCL SCL SDA SDA SDA SDA PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm+ I PCA9671 address map …continued AD1 AD0 SCL SCL SDA V ...

Page 9

... The PCA9671 acknowledges this value only. If the byte is not equal to 06h, the PCA9671 does not acknowledge it. If more than 1 byte of data is sent, the PCA9671 does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a ...

Page 10

... NXP Semiconductors 2 The I C-bus master must interpret a non-acknowledge from the PCA9671 (at any time ‘Software Reset Abort’. The PCA9671 does not initiate a reset of its registers. The unique sequence that initiates a Software Reset is described in Fig 12. Software Reset sequence 7.2.2 Device ID (PCA9671 ID field) The Device ID fi ...

Page 11

... NXP Semiconductors Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. Remark: If the master continues to ACK the bytes after the third byte, the PCA9671 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. ...

Page 12

... PCA9671 acknowledges and the master sends the first data byte for P07 to P00. After the first data byte is acknowledged by the PCA9671, the second data byte P17 to P10 is sent by the master. Once again, the PCA9671 acknowledges the receipt of the data. Each 8-bit data is presented on the port lines after it has been acknowledged by the PCA9671 ...

Page 13

... R/W P05 acknowledge from slave I trt(pu) Rev. 01 — 20 December 2006 PCA9671 data to port P16 acknowledge acknowledge from slave from slave t v(Q) DATA A0 AND B0 VALID ...

Page 14

SCL P0x SDA DATA 00 START condition R/W acknowledge from slave read from port 0 data into port 0 DATA 00 ...

Page 15

SCL P0x SDA DATA 00 START condition R/W acknowledge from slave read from port 0 t h(D) data into port 0 ...

Page 16

... LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm internal Power-On Reset (POR) holds the PCA9671 in DD has reached that point, the reset condition is released DD ...

Page 17

... Remote 16-bit I/O expander for Fm START condition Figure SLAVE SLAVE TRANSMITTER/ RECEIVER TRANSMITTER RECEIVER Rev. 01 — 20 December 2006 P STOP condition 21). MASTER MASTER TRANSMITTER/ MULTIPLEXER RECEIVER SLAVE PCA9671 2 C-bus with reset SDA SCL mba608 2 I C-BUS 002aaa966 © NXP B.V. 2006. All rights reserved ...

Page 18

... SCL from master 1 S START condition 2 C-bus V DD SDA CORE SCL PROCESSOR RESET Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset not acknowledge acknowledge clock pulse for acknowledgement 002aaa987 Figure 23, P00 and P01 are inputs, and P02 P00 ...

Page 19

... Parameter supply voltage supply current ground supply current input voltage input current output current total power dissipation power dissipation per output storage temperature ambient temperature Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset SDA P00 SCL P01 RESET P02 ...

Page 20

... 150 0.5 1 0 PCA9671 2 C-bus with reset Max Unit 5.5 V 500 2.0 V +0. 5 400 mA 300 +0 +0. 5 ...

Page 21

... Product data sheet Remote 16-bit I/O expander for Fm +85 C; unless otherwise specified. amb Conditions Standard-mode 2 I C-bus Min 0 4.7 4.0 4.7 4.0 0 0.3 300 250 4.7 4.0 [4][ and Figure 16 100 Rev. 01 — 20 December 2006 PCA9671 2 Fast-mode I C-bus Plus I Max Min Max 100 0 400 - 1 0.6 - 0.26 - 0.6 - 0.26 - 0 3.45 0.1 0.9 0. ...

Page 22

... MSB (A6) (A7 LOW HIGH 1 /f SCL SU;DAT HD;DAT and Rev. 01 — 20 December 2006 PCA9671 2 STOP bit 0 acknowledge condition (R/W) (A) ( VD;DAT VD;ACK SU;STO 002aab175 ACK or read cycle t rst w(rst) t rst 50 % output off 002aac282 © ...

Page 23

... 0.49 0.32 15.6 7.6 10.65 1.27 0.36 0.23 15.2 7.4 10.00 0.019 0.013 0.61 0.30 0.419 0.05 0.014 0.009 0.60 0.29 0.394 REFERENCES JEDEC JEITA MS-013 Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset detail 1.1 1.1 1.4 0.25 0.25 0.1 0.4 1.0 0.043 0.043 0.055 0.01 0.01 0.004 ...

Page 24

... JEDEC JEITA MO-150 Rev. 01 — 20 December 2006 detail 7.9 1.03 0.9 1.25 0.2 0.13 7.6 0.63 0.7 EUROPEAN PROJECTION PCA9671 2 C-bus with reset SOT340 ( 0.8 8 0.1 o 0.4 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2006. All rights reserved ...

Page 25

... 0.31 0.25 8.8 4.0 6.2 0.635 0.20 0.18 8.6 3.8 5.8 0.012 0.0098 0.344 0.157 0.244 0.025 0.008 0.0075 0.337 0.150 0.228 REFERENCES JEDEC JEITA MO-137 Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset detail ( 0.89 1.05 1 0.25 0.18 0.1 0.41 0.66 0.035 ...

Page 26

... MO-153 Rev. 01 — 20 December 2006 detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9671 2 C-bus with reset SOT355 ( 0.5 8 0.1 o 0.2 0 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2006. All rights reserved ...

Page 27

... 2.5 scale (1) ( 5.6 4.25 3.6 2.25 0.5 4.5 5.4 3.95 3.4 1.95 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 20 December 2006 PCA9671 detail 0.5 1.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION 2 C-bus with reset SOT815-1 ...

Page 28

... 4.1 2.25 4.1 2.25 0.5 2.5 3.9 1.95 3.9 1.95 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 20 December 2006 detail 0.5 2.5 0.1 0.05 0.05 0.1 0.3 EUROPEAN PROJECTION PCA9671 2 C-bus with reset SOT616 ISSUE DATE 01-08-08 02-10-22 © NXP B.V. 2006. All rights reserved ...

Page 29

... Inspection and repair • Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm+ I Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset © NXP B.V. 2006. All rights reserved ...

Page 30

... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 33. Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset Figure 33) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © ...

Page 31

... Least Significant Bit Machine Model Most Significant Bit Programmable Logic Controller Pulse Width Modulation Redundant Array of Independent Disks System Management Bus Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset peak temperature time 001aac844 © NXP B.V. 2006. All rights reserved. ...

Page 32

... Table 10. Revision history Document ID Release date PCA9671_1 20061220 PCA9671_1 Product data sheet Remote 16-bit I/O expander for Fm+ I Data sheet status Change notice Product data sheet - Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset Supersedes - © NXP B.V. 2006. All rights reserved ...

Page 33

... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 20 December 2006 PCA9671 2 C-bus with reset © NXP B.V. 2006. All rights reserved ...

Page 34

... Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1.1 Address maps 7.2 Software Reset call, and device ID addresses . 9 7.2.1 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2.2 Device ID (PCA9671 ID field I/O programming . . . . . . . . . . . . . . . . . . . . . . . 12 8.1 Quasi-bidirectional I/O architecture . . . . . . . . 12 8.2 Writing to the port (Output mode 8.3 Reading from a port (Input mode 8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics of the I 9 ...

Related keywords