PIC12CE67 Microchip Technology, PIC12CE67 Datasheet
PIC12CE67
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PIC12CE67 Summary of contents
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... Memory Device Data Program RAM PIC12CE673 1024 x 14 128 x 8 PIC12CE674 2048 x 14 128 x 8 • 14-bit wide instructions • 8-bit wide data path • Interrupt capability • Special function hardware registers • 8-level deep hardware stack • Direct, indirect and relative addressing modes for ...
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... Analog-to-Digital Converter (A/D) Module ................................................................................................................................... 37 9.0 Special Features of the CPU ....................................................................................................................................................... 45 10.0 Instruction Set Summary.............................................................................................................................................................. 61 11.0 Development Support .................................................................................................................................................................. 75 12.0 Electrical Characteristics for PIC12CE67X .................................................................................................................................. 81 13.0 DC and AC Characteristics - PIC12CE67X ................................................................................................................................. 99 14.0 Packaging Information ............................................................................................................................................................... 103 Index .................................................................................................................................................................................................. 107 PIC12CE67X Product Identification System ..................................................................................................................................... 113 Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at: http://www ...
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... PIC12C67X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class. The PIC12CE67X devices have 128 bytes of RAM, 16 bytes of EEPROM data memory, 5 I/O pins and 1 input pin. In addition a timer/counter is available. Also a 4- channel high-speed 8-bit A/D is provided. The 8-bit res- olution is ideally suited for applications requiring low- cost analog interface, e ...
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... JW, SOIC All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1. DS40181B-page 4 PIC12C672 PIC12CE673 PIC12CE674 ...
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... A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC12CE67X Product Iden- tification System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number. For example, the PIC12CE67X device “ ...
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... PIC12CE67X NOTES: DS40181B-page 6 Preliminary 1998 Microchip Technology Inc. ...
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... ARCHITECTURAL OVERVIEW The high performance of the PIC12CE67X family can be attributed to a number of architectural features com- monly found in RISC microprocessors. To begin with, the PIC12CE67X uses a Harvard architecture, in which program and data are accessed from separate memo- ries using separate buses. This improves bandwidth ...
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... PIC12CE67X FIGURE 3-1: PIC12CE67X BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC12CE673 PIC12CE674 EPROM Program Memory Program 14 Bus Instruction reg Direct Addr 8 Instruction Decode & Start-up Timer Control Timing OSC1/CLKIN Generation OSC2/CLKOUT Internal 4 MHz Clock MCLR Note 1: Higher order bits are from the STATUS register. ...
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... TABLE 3-1: PIC12CE67X PINOUT DESCRIPTION DIP Pin Name # GP0/AN0 7 GP1/AN1/V 6 REF GP2/T0CKI/AN2/INT 5 GP3/MCLR GP4/OSC2/AN3/ 3 CLKOUT GP5/OSC1/CLKIN Legend input output, I/O = input/output power, — = not used, TTL = TTL input Schmitt Trigger input 1998 Microchip Technology Inc. I/O/P Buffer Type Type I/O TTL/ST Bi-directional I/O port/serial programming data/analog input ...
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... PIC12CE67X 3.1 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- gram counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruc- tion is decoded and executed during the following Q1 through Q4. The clocks and instruction execution fl ...
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... RAM. Both Bank 0 and Bank 1 contain special function registers. Some "high use" special function registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access. Also note that F0h through FFh on the PIC12CE67X is mapped into Bank 0 registers 70h-7Fh as common RAM. 4.2.1 GENERAL PURPOSE REGISTER FILE The register fi ...
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... PIC12CE67X FIGURE 4-2: PIC12CE67X REGISTER FILE MAP File Address (1) 00h INDF INDF 01h TMR0 OPTION 02h PCL PCL 03h STATUS STATUS 04h FSR FSR 05h GPIO TRIS 06h 07h 08h 09h 0Ah PCLATH PCLATH 0Bh INTCON INTCON 0Ch PIR1 PIE1 0Dh 0Eh ...
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... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear. 1998 Microchip Technology Inc. Bit 5 ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear. DS40181B-page 14 Bit 5 ...
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... Set Summary." Note 1: Bits IRP and RP1 (STATUS<7:6>) are not used by the PIC12CE67X and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recom- mended, since this may affect upward compatibility with future products ...
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... PIC12CE67X 4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable regis- ter which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on GPIO. FIGURE 4-4: OPTION REGISTER (ADDRESS 81h) R/W-1 R/W-1 R/W-1 R/W-1 INTEDG T0CS T0SE GPPU ...
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... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). R/W-0 R/W-0 R/W-0 R/W-x GPIE T0IF INTF GPIF bit0 Preliminary PIC12CE67X R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset DS40181B-page 17 ...
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... PIC12CE67X 4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the Peripheral interrupts. FIGURE 4-6: PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 — ADIE — — bit7 bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5-0: Unimplemented: Read as '0' ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. U-0 U-0 U-0 U-0 — — — — bit0 Preliminary PIC12CE67X R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset DS40181B-page 19 ...
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... PIC12CE67X 4.2.2.6 PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), an external MCLR Reset, and WDT Reset. FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit ...
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... FIGURE 4-9: OSCCAL REGISTER (ADDRESS 8Fh) R/W-1 R/W-0 R/W-0 R/W-0 CAL5 CAL4 CAL3 CAL2 bit7 bit 7-2: CAL<5:0>: Calibration bit 1-0: Unimplemented, read as 0 1998 Microchip Technology Inc. R/W-0 R/W-0 U-0 U-0 CAL1 CAL0 — — bit0 Preliminary PIC12CE67X R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset DS40181B-page 21 ...
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... PCLATH<4:3>, which are used to access program Opcode <10:0> memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC12CE67X is not recommended since this may affect upward compatibility with future prod- ucts. Preliminary RETLW, and RETFIE instruc- ...
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... An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-11. However, IRP is not used in the PIC12CE67X. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-1. FIGURE 4-11: DIRECT/INDIRECT ADDRESSING ...
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... PIC12CE67X NOTES: DS40181B-page 24 Preliminary 1998 Microchip Technology Inc. ...
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... Any input must be present until read by an input instruction (e.g., MOVF GPIO,W). The outputs are latched and remain unchanged until the output latch is 1998 Microchip Technology Inc. PIC12CE67X rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set ...
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... SCL SDA Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0 unknown unchanged see tables in Section 9.4 for possible values. Note 1: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear. 5.4 I/O Programming Considerations 5.4.1 ...
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... The following bus protocol used with the EEPROM data memory. In this section, the term “pro- cessor” is used to denote the portion of the PIC12CE67X that interfaces to the EEPROM via soft- ware. 1998 Microchip Technology Inc. • Data transfer may be initiated only when the bus is not busy ...
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... PIC12CE67X FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) SCL SDA START CONDITION FIGURE 6-2: ACKNOWLEDGE TIMING SCL SDA Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. ...
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... See Figure 6-4 for flow diagram. FIGURE 6-4: WORD ADDRESS Preliminary PIC12CE67X ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R Did EEPROM NO Acknowledge (ACK = 0)? YES Next Operation ...
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... PIC12CE67X 6.5 READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the EEPROM address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.5.1 CURRENT ADDRESS READ ...
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... MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W T0+2 NT0 NT0 Read TMR0 Read TMR0 Read TMR0 Write TMR0 reads NT0 reads NT0 reads NT0 executed Preliminary PIC12CE67X Data bus 8 TMR0 PSout Set interrupt flag bit T0IF on overflow PC+4 PC+5 PC+6 MOVF TMR0,W NT0 NT0+1 ...
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... PIC12CE67X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1 (Program Counter) PC-1 PC MOVWF TMR0 Instruction Fetch T0 T0+1 TMR0 Instruction Execute FIGURE 7-4: TIMER0 INTERRUPT TIMING OSC1 CLKOUT(3) Timer0 FEh ...
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... Timer0 mod- ule is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing (1) (3) T0 Preliminary PIC12CE67X Small pulse misses sampling DS40181B-page 33 ...
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... PIC12CE67X 7.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer ...
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... INTE GPIE T0IF INTF T0CS T0SE PSA PS2 PS1 TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 Preliminary PIC12CE67X CHANGING PRESCALER (WDT TIMER0) ;Clear WDT and ;prescaler ;prescale value and ;clock source Value on Value on Bit 0 all other POR Resets xxxx xxxx uuuu uuuu GPIF ...
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... PIC12CE67X NOTES: DS40181B-page 36 Preliminary 1998 Microchip Technology Inc. ...
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... Changing ADCON1 register can cause the ) GPIF and INTF flags to be set in the DD pin. The A/D INTCON register. These interrupts should be disabled prior to modifying ADCON1. R/W-0 R/W-0 R/W-0 R/W-0 CHS0 GO/DONE r ADON Preliminary PIC12CE67X R = Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset DS40181B-page 37 ...
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... PIC12CE67X FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 GP4 (1) A 000 A 001 D 010 D 011 D 100 D 101 D 110 D 111 A = Analog input D = Digital I/O Note 1: Value on reset. Note 2: Any instruction that reads a pin configured as an analog input will read a '0'. ...
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... For next conversion step 1 or step 2 as required. The A/D conversion time per bit is defined as T required before next acquisition starts. CHS1:CHS0 V IN (Input voltage 000 or 010 or 100 or 110 or 001 or 011 or 101 PCFG2:PCFG0 Preliminary PIC12CE67X . A minimum wait GP4/AN3 10 GP2/AN2 01 GP1/AN1/V REF 00 GP0/AN0 DS40181B-page 39 ...
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... PIC12CE67X 8.1 A/D Sampling Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 8-4. The source impedance (R ) and the internal sampling switch (R S impedance directly affect the time required to charge the capacitor C ...
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... Device Frequency ) 4 MHz (2) 00 500 (1, time time. AD Preliminary PIC12CE67X will be converted 1.25 MHz 333.33 kHz 1 6 (3) (3) 25 (1,4) ( DS40181B-page 41 ...
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... PIC12CE67X 8.4 A/D Conversions Example 8-2 show how to perform an A/D conversion. The GP pins are configured as analog inputs. The ana- log reference ( the device V REF DD rupt is enabled, and the A/D conversion clock is F The conversion is performed on the GP0 channel. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D ...
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... If the input voltage exceeds the rail values (V by greater than 0.2V, then the accuracy of the conver- sion is out of specification. Note: For the PIC12CE67X, care must be taken when using the GP4 pin in A/D conver- sions due to its proximity to the OSC1 pin. An external RC filter is sometimes added for anti-alias- ing of the input signal ...
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... PIC12CE67X FIGURE 8-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes Yes Start of A/D A/D Clock Conversion Delayed = RC? 1 Instruction Cycle No Yes Abort Conversion Device SLEEP? ADIF = 0 No Finish Conversion SLEEP Power-down A ADIF = 1 Wait TABLE 8-2: SUMMARY OF A/D REGISTERS Address ...
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... CP0 MCLRE bit13 bit 13-8, CP1:CP0: Code Protection bit pairs 6- Code protection off 10 = Locations 400h through 7FEh code protected (do not use for PIC12CE673 Locations 200h through 7FEh code protected 00 = All memory is code protected bit 7: MCLRE: Master Clear Reset Enable bit 1 = Master Clear Enabled ...
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... PIC12CE67X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT modes, the device can have an external clock source drive the GP5/OSC1/CLKIN pin (Figure 9-3) ...
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... R and C components used. Figure 9-6 shows how the R/C combination is resistor connected to the PIC12CE67X. For Rext values below 2 the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g the oscillator becomes sensitive to noise, humidity and leakage ...
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... Table 9-5 for a full description of reset states of all registers. A simplified block diagram of the on-chip reset circuit is shown in Figure 9-7. The PIC12CE67X has a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
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... Ripple-counter OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 1998 Microchip Technology Inc. PIC12CE67X MCLRE INTERNAL MCLR Enable PWRT See Table 9-3 for time-out situations. Enable OST Preliminary S Chip_Reset R Q DS40181B-page 49 ...
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... Then bringing MCLR high will begin execution immediately (Figure 9-9). This is useful for testing purposes or to synchronize more than one PIC12CE67X device oper- ating in parallel. Table 9-5 shows the reset conditions for all the regis- ters ...
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... If wake-up was due to A/D completing then bit all other interrupts generating a wake-up will cause bit wake-up was due to A/D completing then bit all other interrupts generating a wake-up will cause bit 1998 Microchip Technology Inc. PIC12CE67X Program STATUS Counter Register ...
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... PIC12CE67X FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V ...
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... Internal brown-out detection should be disabled, if available, when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. Preliminary PIC12CE67X PROTECTION CIRCUIT 10k MCLR 4.3k PIC12CE67X DD PROTECTION CIRCUIT MCLR 4.3k PIC12CE67X is below a certain level 0.7V V • DS40181B-page 53 ...
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... PIC12CE67X 9.5 Interrupts There are four sources of interrupt: Interrupt Sources TMR0 overflow interrupt External interrupt GP2/INT pin GPIO Port change interrupts (pins GP0, GP1, GP3) A/D Interrupt The interrupt control register (INTCON) records individ- ual interrupt requests in flag bits. It also has individual and global interrupt enable bits ...
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... For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. 1998 Microchip Technology Inc Interrupt Latency 2 PC+1 PC+1 Inst (PC+1) — Dummy Cycle Dummy Cycle Inst (PC) Preliminary PIC12CE67X 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) DS40181B-page 55 ...
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... PIC12CE67X 9.5.1 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 7.0) 9.5.2 INT INTERRUPT External interrupt on GP2/INT pin is edge triggered: either rising if bit INTEDG (OPTION<6>) is set, or fall- ing, if the INTEDG bit is clear ...
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... MUX PSA 0 1 MUX WDT Time-out Bit 7 Bit 6 Bit 5 Bit 4 CP1 CP0 PWRTE INTEDG T0CS T0SE Preliminary PIC12CE67X = Min., Temperature = Max., and DD PS2:PS0 To TMR0 (Figure 7-5) PSA Bit 3 Bit 2 Bit 1 Bit 0 WDTE FOSC2 FOSC1 FOSC0 PSA PS2 PS1 PS0 DS40181B-page 57 ...
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... PIC12CE67X 9.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance) ...
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... Depending on the command, 14-bits of program data are then sup- plied to or from the device, depending if the command was a load or a read. For complete details of serial pro- gramming, please refer to the PIC12CE67X Program- ming Specifications. FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL External ...
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... PIC12CE67X NOTES: DS40181B-page 60 Preliminary 1998 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY Each PIC12CE67X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC12CE67X instruc- tion set summary in Table 10-2 lists byte-oriented, bit- oriented, and literal and control operations. Table 10- 1 shows the opcode fi ...
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... PIC12CE67X 10.1 Special Function Registers as Source/Destination The PIC12CE67X’s orthogonal instruction set allows read and write of all file registers, including special function registers. There are some special situations the user should be aware of: 10.1.1 STATUS AS DESTINATION If an instruction writes to STATUS, the Z, C and DC bits may be set or cleared as a result of the instruction and overwrite the original data bits written ...
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... If this instruction is executed on the TMR0 register (and, where applicable 1), the prescaler will be cleared if assigned to the Timer0 Module Program Counter (PC) is modifi conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 1998 Microchip Technology Inc. PIC12CE67X Cycles 14-Bit Opcode MSb 1 ...
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... PIC12CE67X 10.2 Instruction Descriptions ADDLW Add Literal and W [ label ] ADDLW Syntax: Operands 255 Operation: ( (W) Status Affected: C, DC, Z Encoding: 11 111x Description: The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register Words: 1 Cycles: 1 Example ADDLW ...
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... BTFSC Syntax: Operands: Operation: Status Affected: Encoding: bfff ffff . Description: Words: Cycles: Example bfff ffff 7 Preliminary PIC12CE67X Bit Test, Skip if Clear [ label ] BTFSC f 127 skip if (f<b> None 01 10bb bfff ffff If bit 'b' in register 'f' is '0' then the next instruction is skipped. ...
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... PIC12CE67X BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Encoding: 01 11bb Description: If bit 'b' in register 'f' is '1' then the next instruction is skipped. If bit 'b' is '1', then the next instruction fetched during the current instruction ...
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... DECFSZ Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: 0x13 Example 0x13 0xEC Preliminary PIC12CE67X Decrement f [ label ] DECF f 127 d [0,1] ( (dest 0011 dfff ffff Decrement register 'f the result is stored in the W register the result is stored back in register ...
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... PIC12CE67X GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands 2047 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None Encoding: 10 1kkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two cycle instruction. ...
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... Example 0x91 0x13 0x93 1 MOVWF Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles: Example Preliminary PIC12CE67X Move f [ label ] MOVF f 127 d [0,1] (f) (dest 1000 dfff ffff The contents of register f is moved to a destination dependant upon the sta- tus destination is W reg- ister the destination is fi ...
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... PIC12CE67X NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Encoding: 00 0000 Description: No operation. Words: 1 Cycles: 1 Example NOP OPTION Load Option Register Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION Status Affected: None Encoding: 00 0000 0110 Description: The contents of the W register are loaded in the OPTION register ...
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... Status Affected: Encoding: Description: Words: Cycles: Example: = 1110 0110 = 0 = 1110 0110 = 1100 1100 = 1 Preliminary PIC12CE67X Rotate Right f through Carry [ label ] RRF f 127 d [0,1] See description below C 00 1100 dfff ffff The contents of register 'f' are rotated one bit to the right through the Carry Flag ...
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... PIC12CE67X SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status C, DC, Z Affected: Encoding: 11 110x kkkk Description: The W register is subtracted (2’s com- plement method) from the eight bit literal 'k'. The result is placed in the W register. Words: 1 Cycles: 1 Example 1: SUBLW ...
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... XORWF Syntax: Operands: Operation: 0fff Status Affected: Encoding: Description: Words: Cycles: Example Preliminary PIC12CE67X Exclusive OR Literal with W [ label ] XORLW 255 (W) .XOR 1010 kkkk kkkk The contents of the W register are XOR’ed with the eight bit literal 'k'. ...
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... PIC12CE67X NOTES: DS40181B-page 74 Preliminary 1998 Microchip Technology Inc. ...
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... PIC16C5X, PIC16CXXX and PIC17CXX devices with pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be sup- ported with an adapter socket. PICSTART Plus is CE compliant. 3.x or two versions. Preliminary PIC12CE67X based and max for maximum reliability. It has DD PIC14C000, PIC16C5X, ...
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... PIC12CE67X 11.6 SIMICE Entry-Level Hardware Simulator SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIM- ICE and MPLAB-SIM run under Microchip Technol- ogy’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware simulation for Microchip’ ...
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... MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. 1998 Microchip Technology Inc. PIC12CE67X 11.12 Software Simulator (MPLAB-SIM) The MPLAB-SIM Software Simulator allows code development host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level ...
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... PIC12CE67X 11. Evaluation and EE OQ Programming Tools K L evaluation and programming tools support EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40181B-page 78 Preliminary 1998 Microchip Technology Inc ...
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PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX ü ü ü MPLAB™-ICE ICEPIC Low-Cost ü In-Circuit Emulator MPLAB Integrated ü ü ü Development Environment MPLAB C17* Compiler fuzzy TECH -MP Explorer/Edition ü ü ü Fuzzy Logic Dev. Tool ...
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... PIC12CE67X NOTES: DS40181B-page 80 Preliminary 1998 Microchip Technology Inc. ...
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... ELECTRICAL CHARACTERISTICS FOR PIC12CE67X Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................. .–40 to +125 C Storage temperature ............................................................................................................................. – +150 C Voltage on any pin with respect Voltage on V with respect to V ................................................................................................................ 0 to +7. Voltage on MCLR with respect Total power dissipation (Note 1)...........................................................................................................................700 mW Maximum current out of V pin ...
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... Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. PIC12LCE673-04 PIC12CE673/JW PIC12LCE674-04 PIC12CE674/ 2. ...
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... See section on Power-on Reset for details 0. V/ms See section on Power-on Reset for details 2.7 3.3 mA XT, EXTRC osc configuration DD (PIC12CE67X-04) F OSC 2.7 3.3 mA INTRC osc configuration F OSC - TBD osc configuration (PIC12CE67X-10) F OSC 0.1 0 SCL = 400 kHz - 1.5 TBD A +85 C ...
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... PIC12CE67X 12.2 DC Characteristics: PIC12LCE673-04 (Commercial, Industrial) PIC12LCE674-04 (Commercial, Industrial) DC CHARACTERISTICS Param Characteristic Sym No. D001 Supply Voltage V DD D002* RAM Data Retention V DR Voltage (Note 1) D003 V start voltage POR ensure internal Power-on Reset signal D004* V rise rate VDD ensure internal Power-on Reset ...
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... DC Characteristics: PIC12CE673-04 (Commercial, Industrial, Extended PIC12CE673-10 (Commercial, Industrial, Extended PIC12CE674-04 (Commercial, Industrial, Extended PIC12CE674-10 (Commercial, Industrial, Extended DC CHARACTERISTICS Param Characteristic No. Input Low Voltage I/O ports D030 with TTL buffer D031 with Schmitt Trigger buffer D032 MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) D033 OSC1 (in XT, HS and LP) ...
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... PIC12CE67X DC CHARACTERISTICS Param Characteristic No. Output High Voltage D090 I/O ports/CLKOUT (Note 3) D090A D092 OSC2 D092A Capacitive Loading Specs on Output Pins D100 OSC2 pin D101 All I/O pins and OSC2 † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator confi ...
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... V - TBD 0 TBD Preliminary PIC12CE67X +70˚C (commercial) +85˚C (industrial) Conditions Note1 4.5 V 5.5V DD For V > 5. < 4. For entire V range DD Note1 = 5V PIN Pin at hi- PIN DD impedance V V PIN XT, HS and LP PIN DD osc configuration ...
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... PIC12CE67X DC CHARACTERISTICS Param Characteristic No. Capacitive Loading Specs on Output Pins D100 OSC2 pin D101 All I/O pins and OSC2 † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input not recommended that the PIC12C67X be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specifi ...
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... specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin V SS Preliminary PIC12CE67X DS40181B-page 89 ...
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... All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC12CE67X. DS40181B-page 90 ...
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... Microchip Technology Inc +70 C (commercial), A – +85 C (industrial), A – +125 C (extended) A range is described in Section 10.1 DD (1) Characteristic Min* Typ Frequency TBD 4.00 Frequency TBD 4.00 Preliminary PIC12CE67X Max* Units Conditions TBD MHz V = 5.0V DD TBD MHz V = 2.5V DD DS40181B-page 91 ...
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... DS40181B-page 20, 21 Min — — — — — 0.25T + — TBD TBD PIC12CE67X — PIC12CE67X — Preliminary new value Typ† Max Units Conditions Note Note Note 1 5 ...
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... Watchdog Timer Reset * These parameters are characterized but not tested. † Data in "Typ" column unless otherwise stated. These parameters are for design guidance only and are not tested. 1998 Microchip Technology Inc. PIC12CE67X Min Typ† Max Units 2 — ...
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... PIC12CE67X FIGURE 12-5: TIMER0 CLOCK TIMINGS GP2/T0CKI TMR0 Note: Refer to Figure 12-1 for load conditions. TABLE 12-6: TIMER0 CLOCK REQUIREMENTS Param Sym Characteristic No. 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period 48 Tcke2tmrI Delay from external clock edge to timer increment * These parameters are characterized but not tested ...
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... TABLE 12-8: A/D CONVERTER CHARACTERISTICS: PIC12CE673-04 (COMMERCIAL, INDUSTRIAL, EXTENDED PIC12CE673-10 (COMMERCIAL, INDUSTRIAL, EXTENDED PIC12CE674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED PIC12CE674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED Parameter Sym Characteristic No. N Resolution R N Integral error INT N Differential error DIF N Full scale error FS N Offset error OFF — Monotonicity V Reference voltage ...
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... PIC12CE67X TABLE 12-9: A/D CONVERTER CHARACTERISTICS: PIC12LCE673-04 (COMMERCIAL, INDUSTRIAL) PIC12LCE674-04 (COMMERCIAL, INDUSTRIAL) Parameter Sym Characteristic No. N Resolution R N Integral error INT N Differential error DIF N Full scale error FS N Offset error OFF — Monotonicity V Reference voltage REF V Analog input voltage AIN Z Recommended AIN impedance of ana- ...
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... A/D clock starts. This allows the CY Min Typ† Max 1.6 — 2.0 — 3.0 6.0 9.0 2.0 4.0 6.0 — 9.5T — AD Note 2 20 — cycle. CY Preliminary PIC12CE67X 1 Tcy 1 0 NEW_DATA DONE Units Conditions s V 3.0V REF s V full range REF ADCS1:ADCS0 = 11 (RC oscillator source) s PIC12LCE67X 3. PIC12CE67X — s DS40181B-page 97 ...
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... PIC12CE67X NOTES: DS40181B-page 98 Preliminary 1998 Microchip Technology Inc. ...
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... DC AND AC CHARACTERISTICS - PIC12CE67X The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified V and devices will operate properly only within the specified range. ...
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... PIC12CE67X TABLE 13-1: DYNAMIC I (TYPICAL) - WDT ENABLED Oscillator Frequency External RC Internal *Does not include current through external R&C. FIGURE 13-3: WDT TIMER TIME-OUT PERIOD vs Max +125 C 25 Max + Typ + MIn – (Volts) ...
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... V (Volts) OH 1998 Microchip Technology Inc. FIGURE 13- 2 FIGURE 13- 2.5 3.0 0 Preliminary PIC12CE67X vs 2 Max –40 C Typ +25 C Min +85 C Min +125 C 250.0m 500.0m 1.0 V (Volts Max –40 C Typ +25 C Min +85 C Min +125 C ...
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... PIC12CE67X FIGURE 13- -10 -15 -20 -25 -30 3.5 4.0 4.5 V (Volts) OH DS40181B-page 102 FIGURE 13- 5.0 5.5 0 .25 Preliminary vs 5 Max –40 C Typ +25 C Min +85 C Min +125 C .50 .75 1.0 V (Volts) OL 1998 Microchip Technology Inc. ...
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... For beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1998 Microchip Technology Inc. PIC12CE67X Example 12CE674 04/PSAZ 9725 ...
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... PIC12CE67X Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating Plane Top of Lead to Seating Plane Base to Seating Plane ...
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... A 0.145 0.165 0.185 A1 0.103 0.123 0.143 A2 0.025 0.035 0.045 L 0.130 0.140 0.150 D 0.510 0.520 0.530 E 0.280 0.290 0.300 eB 0.310 0.338 0.365 W 0.161 0.166 0.171 T 0.440 0.450 0.460 U 0.260 0.270 0.280 Preliminary PIC12CE67X MILLIMETERS MIN NOM MAX 7.62 8 2.49 2.54 2.59 0.41 0.46 0.51 1.27 1.40 1.52 0.20 0.25 0.30 3.68 4.19 4.70 2.62 3.12 3.63 0.64 0.89 1.14 3.30 3.56 3.81 12.95 13.21 13.46 7.11 7.37 7.62 7.87 8.57 9.27 4.09 4.34 4.22 11 ...
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... PIC12CE67X NOTES: DS40181B-page 106 Preliminary 1998 Microchip Technology Inc. ...
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... Development Support ..................................................... 3, 75 Development Tools............................................................. 75 Diagrams - See Block Diagrams Digit Carry bit .........................................................................7 Direct Addressing ............................................................... 23 E EEPROM Peripheral Operation .......................................... 27 Electrical Characteristics PIC12CE67X .............................................................. 81 Errata .....................................................................................2 External Brown-out Protection Circuit................................. 53 External Power-on Reset Circuit ........................................ 53 F Family of Devices ..................................................................4 Features ................................................................................1 FSR Register .......................................................... 13, 14, 23 Fuzzy Logic Dev. System ( fuzzy TECH -MP) .................... 77 G General Description ...
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... Paging, Program Memory................................................... 22 PCL..................................................................................... 62 PCL Register .......................................................... 13, 14, 22 PCLATH.............................................................................. 51 PCLATH Register ................................................... 13, 14, 22 PCON Register ............................................................. 20 bit ............................................................................ 15, 48 PIC12CE67X DC and AC Characteristics .......................... 99 PICDEM-1 Low-Cost PICmicro Demo Board ..................... 76 PICDEM-2 Low-Cost PIC16CXX Demo Board................... 76 PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 76 PICSTART Plus Entry Level Development System ......... 75 PIE1 Register...................................................................... 18 Pinout Description PIC12CE67X ...
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... PS2 bit ................................................................................ 16 PSA bit ................................................................................ 16 PUSH .................................................................................. Oscillator ....................................................................... 47 Read Modify Write .............................................................. 26 Read-Modify-Write .............................................................. 26 Register File........................................................................ 11 Registers Map PIC12CE67X ...................................................... 12 Reset Conditions......................................................... 51 Reset............................................................................. 45, 48 Reset Conditions for Special Registers .............................. 51 RETFIE Instruction.............................................................. 70 RETLW Instruction.............................................................. 70 RETURN Instruction ........................................................... 71 RLF Instruction.................................................................... 71 RP0 bit .......................................................................... 11, 15 RP1 bit ................................................................................ 15 RRF Instruction ................................................................... 71 S SEEVAL Evaluation and Programming System ...
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... PIC12CE67X DS40181B-page 110 Preliminary 1998 Microchip Technology Inc. ...
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... Conferences for products, Development Systems, technical information and more • Listing of seminars and events 1998 Microchip Technology Inc. PIC12CE67X Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12CE67X Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
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... PIC12CE67X PRODUCT IDENTIFICATION SYSTEM PART NO. -XX X /XX XXX Pattern: Package: Temperature Range: Frequency Range: Device Please contact your local sales office for exact ordering procedures. SALES AND SUPPORT Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds ...
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... PIC12CE67X NOTES: DS40181B-page 114 Preliminary 1998 Microchip Technology Inc. ...
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... NOTES: 1998 Microchip Technology Inc. PIC12CE67X Preliminary DS40181B-page 115 ...
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... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip ...