PLL500-17 PhaseLink (PLL), PLL500-17 Datasheet
PLL500-17
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PLL500-17 Summary of contents
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... Low jitter (RMS): 2.5ps period jitter. 2.25V to 3.63V DC operation. Available in 8-Pin SOIC or DIE. DESCRIPTION The PLL500- low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources ...
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... Output clock pin. 455.726 P +3.3V VDD power supply pin. Only one VDD pin is necessary. Output Enable input pin. Tri-states output if set to ‘0’. 626.716 I Enables output if set to ‘1’. Internal pull-up. 888.881 I Crystal output pin. SYMBOL V PLL500-17 Preliminary Description MIN. MAX 0 0 ...
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... Frequency change with PWSRR Vdd varied +/- 10% 0V VIN 3.3V, -3dB CONDITIONS with capacitive decoupling between VDD and GND. 36MHz @100Hz offset 36MHz @1kHz offset 36MHz @10kHz offset 36MHz @100kHz offset 36MHz @1MHz offset PLL500-17 Preliminary MIN. TYP. MAX 1.15 3 MIN. ...
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... XIN DD Ouput load of 15pF -12mA 12mA -4mA OHC OH At TTL level Human Body Model SYMBOL MIN. TYP XIN C (xtal PLL500-17 Preliminary MIN. TYP. MAX. 5 2.25 2.4 V – 0 3000 MAX. UNITS 36 MHz 8.5 pF 200 250 ...
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... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Low Phase Noise VCXO (17MHz to 36MHz) TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 2.90 3.10 4.30 4.50 6.20 6.60 0.45 0.75 A1 0.65 BSC B e PART NUMBER PLL500- Marking P500-17 SC P500-17 PLL500-17 Preliminary TEMPERATURE C=COMMERCIAL PACKAGE TYPE S=SOIC D=Die Package Option SOIC - Tape and Reel Die - Waffe Pack Rev 9/17/03 Page 5 ...