S29AL004D SPANSION, S29AL004D Datasheet
S29AL004D
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S29AL004D Summary of contents
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... Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. Publication Number S29AL004D_00 Revision A Amendment 1 Issue Date February 18, 2005 ADVANCE ...
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... Sectors can be locked in-system or via programming equipment — Temporary Sector Unprotect feature allows code changes in previously locked sectors Publication Number S29AL004D_00 Performance Characteristics High performance — Access times as fast Ultra low power consumption (typical values at 5 MHz) — ...
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... However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office S29AL004D range. Changes IO S29AL004D_00_A1 February 18, 2005 ...
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... General Description The S29AL004D Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V supply to perform read, program, and erase operations ...
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... The device electrically erases all bits within a sector simulta- neously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection S29AL004D S29AL004D_00_A1 February 18, 2005 ...
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... Program and Erase Operation Status .............................................. 12 Standby Mode ......................................................................................... 12 Automatic Sleep Mode ......................................................................... 13 RESET#: Hardware Reset Pin ............................................................ 13 Output Disable Mode ........................................................................... 13 Table 2. S29AL004D Top Boot Block Sector Addresses ...........13 Table 3. S29AL004D Bottom Boot Block Sector Addresses ......14 Autoselect Mode ................................................................................... 14 Table 4. S29AL004D Autoselect Codes (High Voltage Method) .......................................................15 Sector Protection/Unprotection ....................................................... 15 Temporary Sector Unprotect ........................................................... 15 Figure 1 ...
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... 2.7–3 Sector Switches Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer X-Decoder S29AL004D S29AL004D DQ0–DQ15 (A-1) Input/Output Buffers Data STB Latch Y-Gating Cell Matrix S29AL004D_00_A1 February 18, 2005 ...
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... RESET RY/BY A17 February 18, 2005 S29AL004D_00_A1 Standard TSOP S29AL004D 48 A16 47 BYTE DQ15/A-1 44 DQ7 43 DQ14 42 DQ6 41 DQ13 40 DQ5 39 DQ12 38 DQ4 DQ11 ...
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... A15 34 A16 33 BYTE DQ15/A-1 30 DQ7 DQ14 29 28 DQ6 27 DQ13 26 DQ5 25 DQ12 24 DQ4 DQ15/A DQ14 DQ13 DQ6 DQ12 V DQ4 DQ10 DQ11 DQ3 DQ8 DQ9 DQ1 CE# OE S29AL004D_00_A1 February 18, 2005 ...
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... Pin Configuration A0–A17 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY Logic Symbol February 18, 2005 S29AL004D_00_A1 addresses = 15 data inputs/outputs = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Selects 8-bit or 16-bit mode = Chip enable = ...
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... Access Speed Access Speed Package Type, Model Material, and Packing Type Number TAI, TFI BAI, BFI 01 (Note 1) MAI, MFI Valid Combinations S29AL004D ° C) Package Description TS048 (Note 2) TSOP VBK048 (Note 3) Fine-Pitch BGA SO044 SOP S29AL004D_00_A1 February 18, 2005 ...
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... The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. trol levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. S29AL004D Device Bus Operations Operation CE# OE# Read L ...
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... Autoselect Mode‚ on page 14 for more information. AC Characteristics‚ on page 37 contains timing specification Write Operation Status‚ on page 26 AC Characteristics‚ on page 37 , but not within V IH S29AL004D CC1 Word/Byte Program has details on erasing a and for for timing diagrams. ± 0.3 V, the device CC S29AL004D_00_A1 February 18, 2005 ...
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... The system can read data t Refer to the tables to Figure 14, on page 38 Output Disable Mode When the OE# input are placed in the high impedance state. Table 2. S29AL004D Top Boot Block Sector Addresses (Sheet Sector A17 A16 A15 SA0 0 0 ...
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... Table 2. S29AL004D Top Boot Block Sector Addresses (Sheet Sector A17 A16 A15 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Table 3. S29AL004D Bottom Boot Block Sector Addresses Sector ...
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... access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in method does not require V on using the autoselect mode. Table 4. S29AL004D Autoselect Codes (High Voltage Method) Description Mode CE# OE# ...
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... Figure 1. Temporary Sector Unprotect Operation Figure 22, on page 45 shows the timing dia- START RESET (Note 1) ID Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) S29AL004D S29AL004D_00_A1 February 18, 2005 ...
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... RESET# Write reset command Sector Protect Sector Protect Algorithm complete Figure 2. In-System Sector Protect/Sector Unprotect Algorithms February 18, 2005 S29AL004D_00_A1 Protect all sectors: The indicated portion of the sector protect algorithm must be ID performed for all unprotected sectors ...
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... The system must provide the CC LKO . and OE during power up, the device does not accept IL IH Table on page 24 AC Characteristics‚ on page S29AL004D Table on page 24 power-up and power-down CE WE defines the valid register 37. for more information S29AL004D_00_A1 February 18, 2005 ...
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... The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program com- mand sequence is initiated by writing two unlock write cycles, followed by the February 18, 2005 S29AL004D_00_A1 section, next. ...
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... for information on these status bits. shows the requirements for the command illustrates the algorithm for the program operation. See for parameters, and Figure 17, on page 42 S29AL004D Table on for timing S29AL004D_00_A1 February 18, 2005 ...
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... The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. February 18, 2005 S29AL004D_00_A1 START Write Program ...
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... Figure 18, on page 43 Table on page 24 29). The time-out begins from the for information on these status bits. illustrates the algorithm for the erase operation. Refer to for parameters, and to Figure 18, on page 43 S29AL004D for timing shows the address and Write for timing S29AL004D_00_A1 February 18, 2005 ...
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... Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. February 18, 2005 S29AL004D_00_A1 for information on these status bits. ...
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... Notes: 1. See Table 12 on page 41 for erase command sequence. 2. See DQ3: Sector Erase Timer‚ on page 29 Table 5. S29AL004D Command Definitions (Sheet Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block ...
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... Table 5. S29AL004D Command Definitions (Sheet Word Sector Erase 6 Byte Erase Suspend (Note 12) 1 Erase Resume (Note 13) 1 Legend Don’t care Address of the memory location to be read Data read from location RA during read operation, and PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first Address of the sector to be verified (in autoselect mode) or erased. Address bits A17– ...
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... Data# Polling algorithm Table 6 on page 31 44, Data# Polling Timings (During AC Characteristics‚ on page 37 shows the outputs for Data# Polling on DQ7. S29AL004D and the following illustrates this. Figure 5, on S29AL004D_00_A1 February 18, 2005 ...
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... Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V February 18, 2005 S29AL004D_00_A1 START Read DQ7–DQ0 ...
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... Figure 18, on page 43 shows the outputs for Toggle Bit I on DQ6. Figure 20, on page 44 shows the differences between DQ2 and S29AL004D 37, Figure shows RY/BY# DQ7: Data# Polling‚ on Figure 6, on page shows the toggle bit DQ2: Toggle Bit II‚ on S29AL004D_00_A1 February 18, 2005 ...
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... When the time-out is complete, DQ3 switches from The system may ignore DQ3 if the system can guarantee that the time between additional February 18, 2005 S29AL004D_00_A1 compare outputs for DQ2 and DQ6. ...
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... Read DQ7–DQ0 Read DQ7–DQ0 No Toggle Bit = Toggle? Yes No DQ5 = 1? Yes (Notes Read DQ7–DQ0 1, 2) Twice Toggle Bit No = Toggle? Yes Program/Erase Operation Not Program/Erase Complete, Write Operation Complete Reset Command Figure 6. Toggle Bit Algorithm 22. S29AL004D Sector Erase S29AL004D_00_A1 February 18, 2005 ...
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... DQ5 switches to 1 when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits‚ on page 29 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. February 18, 2005 S29AL004D_00_A1 Table 6 Table 6. Write Operation Status DQ7 ...
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... Figure 7, on page 33. Maximum DC voltage on input or I/O pins is V +2.0 V for periods ns. See CC Figure 7, on page may cause permanent damage to the device. This ) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C A S29AL004D +0 +0.5 CC Figure 8, 33. Maximum DC input S29AL004D_00_A1 February 18, 2005 ...
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... extended temperature range (>+85°C), typical current is 5µA and maximum current is 10µA. 5. Automatic sleep mode enables the low power mode when addresses remain stable for t 6. Not 100% tested. February 18, 2005 S29AL004D_00_A1 ...
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... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note ° 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 S29AL004D 3000 3500 4000 3 S29AL004D_00_A1 February 18, 2005 ...
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... Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels February 18, 2005 S29AL004D_00_A1 Test C L 6.2 kΩ Figure 11. Test Setup Table 8. Test Specifications Test Condition ...
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... Figure 12. Input Waveforms and Measurement Levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level S29AL004D OUTPUTS Changing, State Unknown 0.5V CC Output S29AL004D_00_A1 February 18, 2005 ...
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... Not 100% tested. 2. See Figure 11, on page 35 and Table 8 on page 35 Addresses CE# OE# WE# Outputs RESET# RY/BY February 18, 2005 S29AL004D_00_A1 Table 9. Read Operations Description Test Setup Read Toggle and Data# Polling for test specifications. t ...
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... Test Setup Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready Figure 14. RESET# Timings S29AL004D All Speed Options Max 20 Max 500 Min 500 Min 50 Min 20 Min S29AL004D_00_A1 February 18, 2005 Unit µ µs ns ...
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... Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV February 18, 2005 S29AL004D_00_A1 Description Max Max Min S29AL004D Speed Options 70 90 Unit ...
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... DQ15 Output t FLQZ t ELFH Data Output Data Output (DQ0–DQ7) (DQ0–DQ14) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications S29AL004D Data Output (DQ0–DQ7) Address Input S29AL004D_00_A1 February 18, 2005 ...
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... CC t Recovery Time from RY/BY Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the Table 12 on page 41 section for more information. February 18, 2005 S29AL004D_00_A1 Description Min Min Min Min Min Min Min Min Min Min ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 17. Program Operation Timings S29AL004D Read Status Data (last two cycles WHWH1 Status D OUT t RB S29AL004D_00_A1 February 18, 2005 ...
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... CC Notes sector address (for Sector Erase Valid Address for reading status data (see page 26). 2. Illustration shows device in word mode. Figure 18. Chip/Sector Erase Operation Timings February 18, 2005 S29AL004D_00_A1 555h for chip erase t AH ...
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... Complement Complement Status Data Status Data Valid Status Valid Status (first read) (second read) S29AL004D VA Valid Data True True Valid Data VA VA Valid Status Valid Data (stops toggling) S29AL004D_00_A1 February 18, 2005 High Z High Z ...
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... Note: Not 100% tested RESET VIDR CE# WE# RY/BY# Figure 22. Temporary Sector Unprotect Timing Diagram February 18, 2005 S29AL004D_00_A1 Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 21. DQ2 vs. DQ6 Table 13. Temporary Sector Unprotect ...
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... For sector protect For sector unprotect Figure 23. Sector Protect/Unprotect Timing Diagram Valid* Valid* 60h Sector Protect: 150 µs Sector Unprotect S29AL004D Valid* Verify 40h Status S29AL004D_00_A1 February 18, 2005 ...
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... WHWH1 WHWH1 (Note Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See Table 15 on page 48 for more information. February 18, 2005 S29AL004D_00_A1 Description Min Min Min Min Min Min Min Min Min Min Min ...
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... Typ (Note 1) Max (Note 2) 0 150 7 210 4.2 12.5 2.9 8.5 ° S29AL004D PA DQ7# D OUT = data OUT Unit Comments s Excludes 00h programming prior to erasure s µs µs Excludes system level overhead (Note 3.0 V, 100,000 cycles, checkerboard CC S29AL004D_00_A1 February 18, 2005 ...
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... Input Capacitance IN C Output Capacitance OUT C Control Pin Capacitance IN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A February 18, 2005 S29AL004D_00_A1 2.7 V, 1,000,000 cycles. CC for further information on command definitions. Test Setup OUT V ...
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... SEE DETAIL A (c) 7 SECTION B-B R (c) GAUGE PLANE θ° 0.25MM (0.0098") BSC C L S29AL004D REVERSE PIN OUT (TOP VIEW 0.08MM (0.0031" WITH PLATING c1 b1 BASE METAL e DETAIL B 3355 \ 16-038.10c S29AL004D_00_A1 February 18, 2005 ...
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... ROW MATRIX SIZE D DIRECTION ME 6 ROW MATRIX SIZE E DIRECTION N 48 TOTAL BALL COUNT fb 0.35 --- 0.43 BALL DIAMETER e 0.80 BSC. BALL PITCH 0.40 BSC. SOLDER BALL PLACEMENT --- DEPOPULATED SOLDER BALLS February 18, 2005 S29AL004D_00_A1 0.10 ( ...
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... Physical Dimensions SO 044—44-Pin Small Outline Package S29AL004D Dwg rev AC; 10/99 S29AL004D_00_A1 February 18, 2005 ...
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... Copyright ©2004-2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies February 18, 2005 S29AL004D_00_A1 ...