s3c2410 Samsung Semiconductor, Inc., s3c2410 Datasheet
s3c2410
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s3c2410 Summary of contents
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... Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture called Advanced Microcontroller Bus Architecture (AMBA). The S3C2410A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length ...
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... Normal mode: Normal operating mode Slow mode: Low frequency clock without PLL Idle mode: The clock for only CPU is stopped. Power-off mode: The Core power including all peripherals is shut down. • Woken up by EINT[15:0] or RTC alarm interrupt from Power-Off mode S3C2410A ...
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... S3C2410A FEATURES (Continued) Interrupt Controller • 55 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, and 1 Battery Fault) • Level/Edge mode on external interrupt source • Programmable polarity of edge and level • Supports Fast Interrupt request (FIQ) for very ...
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... SPI Interface • Compatible with 2-ch Serial Peripheral Interface Protocol version 2.11 • 2x8 bits Shift register for Tx/Rx • DMA-based or interrupt-based operation Operating Voltage Range • Core: 1.8V for 200MHz (S3C2410A-20) 2.0V for 266MHz (S3C2410A-26) • Memory & IO: 3.3V Operating Frequency • 266MHz Package • 272-FBGA ...