S5935 AMCC (Applied Micro Circuits Corp), S5935 Datasheet

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S5935

Manufacturer Part Number
S5935
Description
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

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Part Number S5935
Revision 1.02 – June 27, 2006
S5935
Data Book
PCI Product
S5935
PCI PRODUCT
DATA BOOK
AMCC Confidential and Proprietary
DS1527
1

Related parts for S5935

S5935 Summary of contents

Page 1

... S5935 PCI Product AMCC Confidential and Proprietary S5935 PCI PRODUCT DATA BOOK Part Number S5935 Revision 1.02 – June 27, 2006 Data Book DS1527 1 ...

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... S5935 – PCI Product 2 DS1527 (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...

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... Applied Micro Circuits Corporation (AMCC), the pre- mier supplier of single chip solutions, has developed the S5935 to solve the problem of interfacing applica- tions to the PCI Local bus while offering support for newer PCI chipsets and operating systems. The S5935 is a powerful and flexible PCI controller sup- porting several levels of interface sophistication ...

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... S5935 – PCI Product FEATURES .............................................................................................................................................................. 3 APPLICATIONS ...................................................................................................................................................... 3 DESCRIPTION ........................................................................................................................................................ 3 TABLE OF CONTENTS .......................................................................................................................................... 4 LIST OF FIGURES .................................................................................................................................................. 9 LIST OF TABLES .................................................................................................................................................. 12 S5935 ARCHITECTURE ....................................................................................................................................... 14 S5935 Register Architecture ............................................................................................................................ 14 PCI Configuration Registers ............................................................................................................................ 15 PCI Operation Registers .................................................................................................................................. 15 Add-On Bus Operation Registers .................................................................................................................... 16 Non-Volatile Memory Interface ........................................................................................................................ 16 Mailbox Operation ........................................................................................................................................... 17 Pass-Thru Operation ....................................................................................................................................... 19 FIFO PCI Bus Mastering Operation ................................................................................................................. 19 Signal Type Definition ...................................................................................................................................... 23 NON-VOLATILE MEMORY INTERFACE SIGNALS ...

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... S5935 – PCI Product PCI CONTROLLED BUS MASTER WRITE TRANSFER COUNT REGISTER (MWTC) ..................................... 63 PCI CONTROLLED BUS MASTER READ ADDRESS REGISTER (MRAR) ....................................................... 64 PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) ........................................ 65 MAILBOX EMPTY FULL/STATUS REGISTER (MBEF) ....................................................................................... 66 INTERRUPT CONTROL/STATUS REGISTER (INTCSR) .................................................................................... 68 MASTER CONTROL/STATUS REGISTER (MCSR) ............................................................................................ 72 ADD-ON BUS OPERATION REGISTERS ...

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... S5935 – PCI Product PCI BUS INTERRUPTS ...................................................................................................................................... 114 PCI BUS PARITY ERRORS ................................................................................................................................ 114 ADD-ON BUS INTERFACE ................................................................................................................................. 116 ADD-ON OPERATION REGISTER ACCESSES ................................................................................................ 116 Add-On Interface Signals .............................................................................................................................. 116 System Signals .............................................................................................................................................. 116 Register Access Signals ................................................................................................................................ 116 Asynchronous Register Accesses ................................................................................................................. 117 Synchronous FIFO and Pass-Thru Data Register Accesses ........................................................................ 117 nv Memory Accesses Through the Add-On General Control/Status Register ...

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... Pass-Thru Burst Writes ................................................................................................................................. 156 Pass-Thru Burst Reads ................................................................................................................................. 161 Add-On Pass-Thru Disconnect Operation ..................................................................................................... 165 8-Bit and 16-Bit Pass-Thru Add-On Bus Interface ......................................................................................... 166 CONFIGURATION ............................................................................................................................................... 170 S5935 Base Address Register Definition ...................................................................................................... 170 Creating a Pass-Thru Region ........................................................................................................................ 170 Accessing a Pass-Thru Region ..................................................................................................................... 171 ABSOLUTE MAXIMUM RATINGS ...................................................................................................................... 173 DC CHARACTERISTICS ..................................................................................................................................... 173 AMCC Confidential and Proprietary Revision 1.02 – ...

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... Target Byte-Wide nv Memory Interface Timings ........................................................................................... 189 Target Interrupt Timings ................................................................................................................................ 191 S5935 Pinout and Pin Assignment - 160 PQFP ............................................................................................ 193 S5935 Pinout and Pin Assignment - 208 TQFP ............................................................................................ 194 S5935 Numerical Pin Assignment - 160 PQFP ............................................................................................. 195 Package Physical Dimensions - 160 PQFP .................................................................................................. 197 DOCUMENT REVISION HISTORY ..................................................................................................................... 203 Ordering Information ...

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... Figure 1. S5935 Block Diagram ............................................................................................................................... 3 Figure 2. ................................................................................................................................................................ 14 Figure 3. ................................................................................................................................................................ 18 Figure 4. ................................................................................................................................................................ 19 Figure 5. ................................................................................................................................................................ 20 Figure 6. S5933 Pin Assignment ........................................................................................................................... 21 Figure 7. S5935 Signal Pins .................................................................................................................................. 23 Figure 8. Vendor Identification Register ................................................................................................................. 34 Figure 9. Device Identification Register ................................................................................................................. 35 Figure 10. PCI Command Register ........................................................................................................................ 36 Figure 11. PCI Status Register .............................................................................................................................. 38 Figure 12. Revision Identification Register ............................................................................................................ 40 Figure 13. .............................................................................................................................................................. 41 Figure 14 ...

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... Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target) ......................................... 105 Figure 51. Master-Initiated, Normal Completion (S5935 as either Target or Initiator) ......................................... 105 Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5935 as Master) ........ 106 Figure 53. Master Initiated Termination Due to Preemption and Latency Timer Expired (S5935 as Master) ...... 106 Figure 54 ...

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... Figure 108. nv Memory Write Timing ................................................................................................................... 190 Figure 109. IRQ# Interrupt Output Timing ........................................................................................................... 191 Figure 110. Mailbox 4, Byte 3 Direct Input Timing ............................................................................................... 191 Figure 111. S5935 - 160 PQFP Package Drawing .............................................................................................. 197 Figure 112. S5935 - Marking Drawing ................................................................................................................. 198 Figure 113. Package Physical Dimension - 208 TQFP ........................................................................................ 202 AMCC Confidential and Proprietary Revision 1.02 – ...

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... S5935 – PCI Product Table 1. PCI Configuration Registers .................................................................................................................... 15 Table 2. PCI Operation Registers .......................................................................................................................... 16 Table 3. Add-On Bus Operation Registers ............................................................................................................ 17 Table 4. Configuration Registers ........................................................................................................................... 32 Table 5. Vendor Identification Register .................................................................................................................. 34 Table 6. Device Identification Register .................................................................................................................. 35 Table 7. PCI Command Register ........................................................................................................................... 37 Table 8. PCI Status Register ................................................................................................................................. 39 Table 9. Revision Identification Register ................................................................................................................ 40 Table 10. Defined Base Class Codes .................................................................................................................... 41 Table 11 ...

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... S5935 – PCI Product Table 41. Supported PCI Bus Commands ........................................................................................................... 101 Table 42. Target Termination Types .................................................................................................................... 109 Table 43. Possible Combinations of FRAME# and IRDY# .................................................................................. 112 Table 44. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write) .................................................... 168 Table 45. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read) .................................................... 168 AMCC Confidential and Proprietary Revision 1.02 – ...

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... FIFO data channel under either Host or Add-On software control or Add- On hardware control using dedicated S5935 signal pins. The S5935 signal pins are shown in Figure 2. The PCI Local Bus signals are detailed on the left side; Add-On 14 DS1527 Revision 1.02 – ...

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... The S5935 can either load these registers with default values or initialize them from an external non-volatile memory area called ‘Configura- tion Space’. The S5935 can accommodate a total of 256 bytes of external memory for this purpose. The first 64 bytes is reserved for user defined configuration data which is loaded into the PCI Configuration Regis- ters during power-up initialization ...

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... Offset Bus Master Control/Status Register (MCSR) 00h Non-Volatile Memory Interface 04h The S5935 contains a set of PCI Configuration Regis- 08h ters. These registers can be initialized with default 0Ch values or with designer specified values contained in an external nvRAM. The nvRAM can be either a serial ...

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... S5935 – PCI Product The optional nvRAM allows the Add-On card manufac- turer to initialize the S5935 with his specific Vendor ID and Device ID numbers along with desired S5935 operation characteristics. The non-volatile memory feature also provides for the Expansion BIOS and POST code (power-on-self-test) options on the PCI bus ...

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... S5935 – PCI Product Figure 3. 18 DS1527 S5935 PCI MB1 PCI MB2 PCI MB3 PCI MB4 Byte 0 Byte 0 Byte 0 Byte 0 PCI MB1 PCI MB2 PCI MB3 PCI MB4 Byte 1 Byte 1 Byte 1 Byte 1 PCI MB1 PCI MB2 PCI MB3 PCI MB4 Byte 2 ...

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... The Pass-Thru data channel utilizes sep- arate Add-On bus signal pins to reflect a PCI bus read or write request. Add-On logic decodes these signals to determine if it must read or write data to the S5935 to satisfy the request. Information decoded includes PCI request occurring, the byte lanes involved, the specific Pass-Thru region accessed and if the request is a burst or single-cycle access ...

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... S5935 – PCI Product Figure 5. 20 DS1527 S5935 Endian Converter Converter 32-Bit Master Write Address Register ...

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... S5935 – PCI Product Figure 6. S5933 Pin Assignment 56 AD0 55 AD1 54 AD2 52 AD3 48 AD4 47 AD5 46 AD6 44 AD7 42 AD8 40 AD9 39 AD10 38 AD11 36 AD12 35 AD13 34 AD14 32 AD15 14 AD16 12 AD17 8 AD18 7 AD19 6 AD20 4 AD21 3 AD22 2 AD23 158 AD24 156 AD25 155 AD26 154 AD27 152 ...

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... S5935 – PCI Product 22 DS1527 (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...

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... Open Drain allows multiple devices to share as a wire-OR. o/d Note that a # symbol at the end of a signal name denotes that the active state occurs when the signal low voltage. When no # symbol is present, the signal is active high. Figure 7. S5935 Signal Pins S5935 Control AMCC Confidential and Proprietary ...

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... S5935 – PCI Product Address and Data Pins — PCI Local Bus Signal Type AD[31:00] t/s Local Bus Address/Data lines. Address and data are multiplexed on the same pins. Each bus opera- tion consists of an address phase followed by one or more data phases. Address phases are identified when the control signal, FRAME#, is asserted ...

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... Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop the current transaction. LOCK# in Lock. The lock signal provides for the exclusive use of a resource. The S5935 may be locked as a tar- get by one master at a time. The S5935 cannot lock a target when master. IDSEL in Initialization Device Select ...

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... S5935 – PCI Product Error Reporting Pins — PCI Local Bus Signal Type SERR# o/d System Error. This pin is used for reporting address parity errors, data parity errors on Special Cycle com- mands, or any error condition having a catastrophic system impact. Interrupt Pin — PCI Local Bus ...

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... External memory data bus. These pins are used to directly connect with the data pins of an external non-volatile memory. When a serial memory is connected to the S5935, the pins EQ4, EQ5, EQ6 and EQ7 become reconfigured to provide signal pins for bus mastering control from the Add-On interface. ...

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... S5935 – PCI Product ADD-ON BUS INTERFACE SIGNALS The following sets of signals represent the interface pins available for the Add-On function. There are four Register Access Pins Signal Type DQ[31:00] t/s Datapath DQ0–DQ31. These pins represent the datapath for the Add-On peripheral’s data bus. They provide the interface to the controller’ ...

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... ADR[6:2] and the byte enables BE[3:0]#. MODE in This pin control whether the S5935 data accesses on the DQ bus are to be 32-bits wide (MODE = low) or 16-bits wide (MODE = high). When in the 16 bit mode, the signal BE3# is reassigned as the address signal ADR1. FIFO Access Pins ...

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... S5935 – PCI Product Pass-Thru Interface Pins Signal Type PTADR# in Pass-Thru Address. This signal causes the actual Pass-Thru requested address to be presented as outputs on the DQ pins DQ[31:0] for Add-Ons with 32-bit buses, or the low-order 16 bits for Add-Ons with 16-bit buses necessary that all other bus control signals be in their inactive state during the assertion of PTADR# ...

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... S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 31 ...

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... S5935 – PCI Product PCI CONFIGURATION REGISTERS Each PCI bus device contains a unique 256-byte region called its configuration header space. Portions of this configuration header are mandatory in order for a PCI agent full compliance with the PCI spec- Table 4. Configuration Registers Configuration Address Offset 00h– ...

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... S5935 – PCI Product PCI Configuration Space Header DEVICE ID STATUS BIST MAX_LAT LEGEND EPROM IS DATA SOURCE (READ ONLY) CONTROL FUNCTION EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT) EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT) HARD-WIRED TO ZEROES Note: Some registers are a combination of the above. See individual sections for full description ...

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... S5935 – PCI Product VENDOR IDENTIFICATION REGISTER (VID) Vendor Identification Register Name 00h-01h Address Offset 10E8h (AMCC, Applied Micro Cir- Power-up value cuits Corp.) External nvRAM offset 040h-41h Boot-load Read Only (RO) Attribute 16 bits Size Figure 8. Vendor Identification Register 15 Table 5. Vendor Identification Register ...

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... S5935 – PCI Product DEVICE IDENTIFICATION REGISTER (DID) Device Identification Register Name 02h-03h Address Offset 4750h (ASCII hex for ‘GP’, General Power-up value Purpose) External nvRAM offset 042h-43h Boot-load Read Only Attribute 16 bits Size Figure 9. Device Identification Register 15 Table 6. Device Identification Register ...

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... S5935 – PCI Product PCI COMMAND REGISTER (PCICMD) PCI Command Register Name 04h-05h Address Offset 0000h Power-up value not used Boot-load Read/Write (R bits, Read Attribute Only for all others) 16 bits Size Figure 10. PCI Command Register 15 Reserved = 00's Fast Back-to-Back SERRE ...

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... The S5935 controller does not monitor (or generate) special cycles and this bit is hardwired Bus Master Enable. This bit, when set to a one, allows the S5935 controller to function as a bus master. This bit is initialized to 0 upon the assertion of signal pin RESET#. ...

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... S5935 – PCI Product PCI STATUS REGISTER (PCISTS) PCI Status Register Name 06h-07h Address Offset 0080h Power-up value not used Boot-load Read Only (RO), Read/Write Clear Attribute (R/WC) 16 bits Size Figure 11. PCI Status Register DS1527 This 16-bit register contains the PCI status informa- tion ...

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... Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involving the S5935 device as the master. The Parity Error Enable bit (D6 of the Command Register) must be set in order for this bit to be set. ...

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... S5935 – PCI Product REVISION IDENTIFICATION REGISTER (RID) Revision Identification Register Name 08h Address Offset 00h Power-up value External nvRAM/EPROM offset 048h Boot-load Read Only Attribute 8 bits Size Figure 12. Revision Identification Register 7 Table 9. Revision Identification Register Bit 7:0 Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h ...

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... S5935 – PCI Product CLASS CODE REGISTER (CLCD) Class Code Register Name 09h-0Bh Address Offset FF0000h Power-up value External nvRAM offset 049h-4Bh Boot-load Read Only Attribute 24 bits Size Figure 13. @0Bh 7 Base Class Table 10. Defined Base Class Codes Base-Class 00h Early, pre-2.0 PCI specification devices ...

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... S5935 – PCI Product Table 11. Base Class Code 00h: Early, Pre-2.0 Specification Devices Sub-Class 00h 01h Table 12. Base Class Code 01h: Mass Storage Controllers Sub-Class 00h 01h 02h 03h 04h 80h Table 13. Base Class Code 02h: Network Controllers Sub-Class 00h 01h ...

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... S5935 – PCI Product Table 17. Base Class Code 06h: Bridge Devices Sub-Class 00h 01h 02h 03h 04h 05h 06h 07h 80h Table 18. Base Class Code 07h: Simple Communications Controllers Sub-Class 00h 01h 80h Table 19. Base Class Code 08h: Base System Peripherals ...

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... S5935 – PCI Product Table 21. Base Class Code 0Ah: Docking Stations Sub-Class 00h 80h Table 22. Base Class Code 0Bh: Processors Sub-Class 00h 01h 02h 10h 40h Table 23. Base Class Code 0Ch: Serial Bus Controllers Sub-Class 00 01h 02h 44 DS1527 Prog I/F 00h Generic docking station ...

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... S5935 – PCI Product CACHE LINE SIZE REGISTER (CALN) Cache Line Size Register Name 0Ch Address Offset 00h, hardwired Power-up value not used Boot-load Read Only Attribute 8 bits Size Figure 14. Cache Line Size Register 7 AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 This register is hardwired to 0 ...

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... S5935 – PCI Product LATENCY TIMER REGISTER (LAT) Latency Timer Register Name 0Dh Address Offset 00h Power-up value External nvRAM offset 04Dh Boot-load Read/Write, bits 7:3; Read Only bits Attribute 2:0 8 bits Size Figure 15. Latency Timer Register DS1527 The latency timer register has meaning only when this ...

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... This register consists of two fields: Bits 6:0 define the format for bytes 10h through 3Fh of the device config- uration header, and bit 7 establishes whether this device represents a single function (bit mul- tifunction (bit PCI bus agent. The S5935 is a single function PCI device ...

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... S5935 – PCI Product BUILT-IN SELF-TEST REGISTER (BIST) Built-in Self-Test Register Name 0Fh Address Offset 00h Power-up value External nvRAM/EPROM offset 04Fh Boot-load D7, D5-0 Read Only PCI bus Attribute write only 8 bits Size Figure 17. Built-In Self Test Register Table 24. Built-In Self-Test Register ...

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... S5935 – PCI Product BASE ADDRESS REGISTERS (BADR) Base Address Register Name 10h, 14h, 18h, 1Ch, 20h, 24h Address Offset FFFFFFC1h for offset 10h; Power-up value 00000000h for all others External nvRAM offset 050h, 54h, Boot-load 58h, 5Ch, 60h (BADR0-4) high bits Read/Write; low bits Read ...

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... S5935 – PCI Product Table 25. Base Address Register — Memory (Bit Bit Description 31:4 Base Address Location. These bits are used to position the decoded region in memory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Except for Base Address Register 0, these bits are individually enabled by the contents sourced from the external boot memory ...

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... S5935 – PCI Product Table 26. Read Response (Memory Assigned All-Ones Write Operation to a Base Address Register Response 00000000h none - disabled FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFC0h 64 bytes (16 DWORDs) FFFFFF80h 128 bytes (32 DWORDs) FFFFFF00h 256 bytes (64 DWORDs) FFFFFE00h 512 bytes (128 DWORDs) ...

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... S5935 – PCI Product Table 27. Read Response (I/O Assigned All-Ones write Operation to a Base Address Register Response 00000000h none - disabled FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFF9h 8 bytes (2 DWORDs) FFFFFFF1h 16 bytes (4 DWORDs) FFFFFFE1h 32 bytes (8 DWORDs) FFFFFFC1h 64 bytes (16 DWORDs) FFFFFF81h 128 bytes (32 DWORDs) FFFFFF01h 256 bytes (64 DWORDs) 1. BADR5 register is not implemented and will return all 0’ ...

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... S5935 controllers’ external BIOS ROM (or nvRAM) interface. Since PCI bus accesses to the ROM may be 32 bits wide, repeated operations to the ROM are generated by the S5935 and the wider data is assembled internal to the S5935 controller and then transferred to the PCI bus by the S5935. 11 ...

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... S5935 – PCI Product Table 29. Read Response to Expansion ROM Base Address Register (after all-ones written) Response 00000000h none - disabled FFFFF801h 2K bytes (512 DWORDs) FFFFF001h 4K bytes (1K DWORDs) FFFFE001h 8K bytes (2K DWORDs) FFFFC001h 16K bytes (4K DWORDs) FFFF8001h 32K bytes (8K DWORDs) FFFF0001h 64K bytes (16K DWORDs) ...

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... AMCC Confidential and Proprietary This register indicates the interrupt routing for the S5935 controller. The ultimate value for this register is system-architecture specific. For x86 based PCs, the values in this register correspond with the established interrupt numbers associated with the dual 8259 con- trollers used in those machines ...

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... S5935 – PCI Product INTERRUPT PIN REGISTER (INTPIN) Interrupt Pin Register Name 3Dh Address Offset 01h Power-up value External nvRAM offset 7Dh Boot-load Read Only Attribute 8 bits Size Figure 21. Interrupt Pin Register DS1527 This register identifies which PCI interrupt, if any, is connected to the controller’ ...

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... S5935 – PCI Product MINIMUM GRANT REGISTER (MINGNT) Minimum Grant Register Name 3Eh Address Offset 00h Power-up value External nvRAM offset 7Eh Boot-load Read Only Attribute 8 bits Size Figure 22. Minimum Grant Register AMCC Confidential and Proprietary This register may be optionally used by bus masters to specify how long a burst period the device needs ...

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... S5935 – PCI Product MAXIMUM LATENCY REGISTER (MAXLAT) Maximum Latency Register Name 3Fh Address Offset 00h Power-up value External nvRAM offset 7Fh Boot-load Read Only Attribute 8 bits Size Figure 23. Maximum Latency Register DS1527 This register may be optionally used by bus masters to specify how often this device needs PCI bus access ...

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... S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 59 ...

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... S5935 – PCI Product The PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space (I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communication between the PCI and Add-On buses. Data, software-defined commands and command Table 30. Operation Registers — ...

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... Add-On’s interrupt control/status register. Mailbox 4, byte 3 only exists as device pins on the S5935 devices when used with a serial non- volatile memory. This location provides access to the bidirectional FIFO. Separate registers are used when reading from or writing to the FIFO ...

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... Also, the PCI bus address bit A1 will always be zero when this controller is the bus master. This signifies to the target that the S5935 controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. ...

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... AMCC Confidential and Proprietary The master write transfer count register is used to con- vey to the S5935 controller the actual number of bytes that are to be transferred. The value in this register is decremented with each bus master PCI write opera- tion until the transfer count reaches zero. ...

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... Reading of this register during a transfer process (done when the S5935 controller is functioning as a target—i.e., not a bus master) is permitted and may be used to monitor the progress of the transfer. During the address phase ...

Page 65

... S5935 – PCI Product PCI CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) Master Read Transfer Count Register Name 30h PCI Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size Figure 27. PCI Controlled Bus Master Read Transfer Count Register AMCC Confidential and Proprietary Revision 1.02 – ...

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... S5935 – PCI Product MAILBOX EMPTY FULL/STATUS REGIS- TER (MBEF) Mailbox Empty/Full Status Register Name 34h PCI Address Offset 00000000h Power-up value Read Only Attribute 32 bits Size Figure 28. Mailbox Empty/Full Status Register 31 66 DS1527 This register provides empty/full visibility of each byte within the mailboxes ...

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... S5935 – PCI Product Table 31. Mailbox Empty/Full Status Register Bit 31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been written by the Add-On interface but have not yet been read by the PCI bus. Each bit location corresponds to a specific byte within one of the four incoming mailboxes ...

Page 68

... S5935 – PCI Product INTERRUPT CONTROL/STATUS REGIS- TER (INTCSR) Interrupt Control and Status Register Name PCI Address 38h Offset 00000000h Power-up value Read/Write (R/W), Read/ Attribute Write_One_Clear (R/WC) 32 bits Size Figure 29. Interrupt Control/Status Register FIFO and Endian Control Interrupt Asserted (RO) Target Abort (R/WC) ...

Page 69

... S5935 – PCI Product Figure 30. FIFO Management and Endian Control Byte OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT BYTE 4-7 (NOTE1) INBOUND FIFO ADD-ON PCI DWORD TOGGLE 0 = BYTES 0-3 (DEFAULT BYTE 4-7 NOTE 1: D24 and D25 MUST BE ALSO "1" AMCC Confidential and Proprietary Revision 1.02 – ...

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... Target Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a target abort during a PCI bus cycle while the S5935 was the current bus master. This bit operates as read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a write to this bit with the data of “zero” will not change the state of this bit ...

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... S5935 – PCI Product Table 32. Interrupt Control/Status Register (Continued) Bit 4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailbox register identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write. 3:2 Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes the source for causing an outgoing mailbox interrupt ...

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... S5935 – PCI Product MASTER CONTROL/STATUS REGISTER (MCSR) Master Control/Status Register Name PCI Address 3Ch Offset 000000E6h Power-up value Read/Write, Read Only, Write Attribute Only Size32 bits This register provides for overall control of this device used to enable bus mastering for both data direc- tions as well as providing a method to perform software resets ...

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... Enable memory read multiple during S5935 bus mastering mode. 14 Read Transfer Enable. This bit must be set to a one for S5935 PCI bus master read transfers to take place. Writing a zero to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero. ...

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... Write FIFO management scheme. When set to a one this bit causes the controller to refrain from requesting the PCI bus unless it has four or more FIFO locations filled. Once the S5935 controller is granted the PCI bus pos- session of the bus due to the write channel, this constraint is not meaningful. When this bit is zero the controller will request the PCI bus if it has at least one valid FIFO word ...

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... S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 75 ...

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... S5935 – PCI Product ADD-ON BUS OPERATION REGISTERS The Add-On bus interface provides access to 18 DWORDs (72 bytes) of data, control and status infor- mation. All of these locations are accessed by asserting the Add-On bus chip select pin (SELECT#) in conjunction with either the read or write control strobes (signal pin RD# or WR#) ...

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... Writing to one of these registers can optionally cause a PCI bus interrupt (if desired) when the PCI interrupt control/status register is properly configured. Mailbox 4, byte 3 only exists as device pins on the S5935 device when used with a serial nonvolatile memory. This byte is not available if a byte-wide nv memory is used. ...

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... Also, the PCI bus address bit A1 will always be zero when this controller is the bus master. This signifies to the target that the S5935 controller is burst capable and that the target should not arbitrarily disconnect after the first data phase of this operation. ...

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... S5935 – PCI Product ADD-ON PASS-THRU ADDRESS REGISTER (APTA) Register Add-On Pass-Thru Address Name Add-On 28h Address Offset Power-up XXXXXXXXh value Read Only Attribute 32 bits Size ADD-ON PASS-THRU DATA REGISTER (APTD) Add-On Pass-Thru Data Register Name Add-On 2Ch Address Offset XXXXXXXXh ...

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... Reading of this register during a transfer process (done when the S5935 controller is functioning as a target—i.e., not a bus master) is permitted and may be used to monitor the progress of the transfer. During the address phase ...

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... S5935 – PCI Product ADD-ON EMPTY/FULL STATUS REGISTER (AMBEF) Add-On Mailbox Empty/Full Status Register Name Add-On 34h Address Offset 00000000h Power-up value Read Only Attribute 32 bits Size Figure 34. Add-On Mailbox Empty/Full Status Register 31 AMCC Confidential and Proprietary This register provides empty/full visibility of each byte within the mailboxes ...

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... S5935 – PCI Product Table 35. Add-On Mailbox Empty/Full Status Register Bit 31:16 Outgoing Mailbox Status. This field indicates which outgoing mailbox registers have been written by the Add-On bus interface but have not yet been read by the PCI bus. Each bit location corresponds to a specific byte within one of the four outgoing mailboxes ...

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... S5935 – PCI Product ADD-ON INTERRUPT CONTROL/STATUS REGISTER (AINT) Add-On Interrupt Control and Status Register Name Add-On 38h Address Offset 00000000h Power-up value Read/Write, Read/Write_One_Clear Attribute 32 bits Size Figure 35. Add-On Interrupt Control/Status Register Interrupt Status ...

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... Master/Target Abort. This bit signifies that an interrupt has been generated due to the S5935 encountering a Master or Target abort during an S5935 initiated PCI bus cycle. This bit operates as read or write one clear. Writing a one to this bit causes cleared. Writing a zero to this bit does nothing. ...

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... S5935 – PCI Product Table 36. Interrupt Control/Status Register (Continued) Bit 3:2 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write. ...

Page 86

... S5935 – PCI Product ADD-ON GENERAL CONTROL/STATUS REGISTER (AGCSTS) Add-On General Control and Status Register Name Add-On 3Ch Address Offset 000000F4h (PCI initiated bus master- ing) 00000034h (Add-On initiated bus Power-up value mastering) Read/Write, Read Only, Write Only Attribute 32 bits Size Figure 36 ...

Page 87

... S5935 – PCI Product Table 37. Add-On General Control/Status Register Bit 31:29 nvRAM/EPROM Access Control. This field provides a method for access to the optional, external non-volatile mem- ory. Write operations are achieved by a sequence of byte operations involving these bits and the 8-bit field of bits 23 through 16 ...

Page 88

... S5935 – PCI Product Table 37. Add-On General Control/Status Register (Continued) Bit 6 PCI to Add-On Transfer Count Equals Zero (RO). This bit as a one signifies that the read transfer count is all zeros. Only when Add-On initiated bus mastering is enabled. 5 PCI to Add-On FIFO Empty. This bit when the PCI to Add-On FIFO is empty. ...

Page 89

... This register is only accessible when Add-On initiated bus mastering is enabled. The master write transfer count register is used to con- vey to the S5935 controller the actual number of bytes that are to be transferred. The value in this register is decremented with each bus master PCI write opera- tion until the transfer count reaches zero ...

Page 90

... S5935 – PCI Product ADD-ON CONTROLLED BUS MASTER READ TRANSFER COUNT REGISTER (MRTC) Master Read Transfer Count Register Name Add-On 5Ch Address Offset 00000000h Power-up value Read/Write Attribute 32 bits Size Figure 38. Add-On Controlled Bus Master Read Transfer Count Register ...

Page 91

... S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 91 ...

Page 92

... I/O space requirements. These allow the PCI BIOS to enable the device and locate it within sys- tem memory or I/O space. After a PCI reset, the S5935 can be configured for a specific application by downloading device setup infor- mation from an external non-volatile memory into the device Configuration Registers. The S5935 can also be used in a default configuration, with no external boot device ...

Page 93

... PCI controller and the external serial memory: a serial clock pin, SCL, and a serial data pin, SDA. The serial clock pin is an output from the S5935, and the serial data pin is bidirectional. The serial clock is derived by dividing the PCI bus clock by 512. This means that the frequency of the serial clock is approximately 65 kHz for a 33-MHz PCI bus clock ...

Page 94

... S5935 – PCI Product Figure 39. Serial Interface Definition of Start and Stop SCL SDA START BIT Figure 40. Serial Interface Clock/Data Relationship SCL SDA Figure 41. Serial Interface Byte Access — Write ADDRESS R T 1010 Figure 42. Serial Interface Byte Access — Read S T SLAVE ...

Page 95

... Type 1 configuration cycles are intended only for bridge devices and have AD0 with AD1 during the address phase. The S5935 PCI device is a bus agent (not a bridge) and responds only to a Type 0 configuration accesses. Figure 5 depicts the state of the AD bus during the address phase of a Type 0 configuration access ...

Page 96

... S5935 – PCI Product Figure 44. Type 0 Configuration Read Cycles 1 PCI CLOCK (I) FRAME # AD [31:0] ADDRESS (I) CONFIG. READ CMD C/BE [3:0]# (I) (I) IRDY# (T) TRDY# IDSEL (I) (T) DEVSEL# SELECT CONDITION Figure 45. Type 0 Configuration Write Cycles 1 PCI CLOCK (I) FRAME # AD [31:0] ADDRESS (I) CONFIG WRITE CMD C/BE [3:0]# (I) (I) IRDY# (T) TRDY# (I) IDSEL (T) DEVSEL# ...

Page 97

... The following represents the boot-load image for the S5935 controller’s PCI configuration register: 40h 2 [your vendor ID] 42h 2 [your device ID] 44h 1 not used 45h 1 [Bus Master Config.] 46h 2 not used ...

Page 98

... If a valid external nv memory is identified by the S5935, the PCI data structure is used to configure the S5935. The PCI data structure is not necessary for this device to operate external nv memory is imple- mented, the S5935 boots with the default configuration values ...

Page 99

... S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 99 ...

Page 100

... Table 1 lists the PCI commands and identifies those which are supported by the S5935 controller as a target and those which may be pro- duced by the S5935 controller as an initiator. A “Yes” in the “Supported As Target” column in Table 1 indi- cates t he S5935 cont roller as serts the signal DEVSEL# when that command is issued along with the appropriate PCI address ...

Page 101

... S5935 – PCI Product Table 41. Supported PCI Bus Commands C/BE[3:0]# 0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write 0100 Reserved 0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple ...

Page 102

... The S5935 com- pletes the initial data phase successfully, but asserting STOP# indicates that the next access needs completely new cycle. Accesses to memory or I/O Figure 46. Zero Wait State Burst Read PCI Bus Transfer (S5935 as Initiator) 12 PCI CLOCK (I) ...

Page 103

... There is only one condition where accesses to S5935 operation registers do not return TRDY# but do assert STOP#. This is called a target-initiated termination or Figure 47. Single Data Phase PCI Bus Read of S5935 Registers (S5935 as Target) 1 (I) FRAME # AD [31:0] ...

Page 104

... Figure 4). TRDY# is not driven until the target has accepted the data for the PCI write. When the S5935 becomes the PCI initiator, it attempts sus- Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5935 as Initiator) 1 PCI CLOCK FRAME # ...

Page 105

... This is called initiator preemption and is discussed in later Sections. When the S5935 is an initiator and does not observe a DEVSEL# response to its assertion of FRAME#, it ter- minates the cycle (master abort). Figure 50. Single Data Phase PCI Bus Write of S5935 Registers (S5935 as Target) 1 PCI CLOCK FRAME # (I) ...

Page 106

... The S5935 Master Latency Timer register con- trols the S5935 responsiveness to the removal of a bus grant (preemption). The presence of a Master Figure 52. Master Initiated Termination Due to Preemption and Latency Timer Active (S5935 as Master) 1 PCI CLOCK GNT # ...

Page 107

... FRAME# (if asserted) upon the sixth clock period (Fig- ure 9). IRDY# is deasserted by the S5935 during the next clock. The occurrence of a master abort causes the S5935 to set bit 13 (Master Abort) of the PCI Sta- tus Register, indicating an error condition. Target-Initiated Termination There are situations where the target may end a trans- fer prematurely. This is called “ ...

Page 108

... IRDY# is asserted. This situation can only occur when the S5935 is a target. When the S5935 is an initiator, IRDY# is always asserted during the data phase (no initiator wait states). The timing diagram in Figure 10b applies to the S5935 as either a target disconnecting or an initiator with its target performing a disconnect ...

Page 109

... The S5935 configuration and operation regis- ters never respond with a target abort when accessed. If the S5935 encounters this condition when operating as a PCI initiator, the S5935 sets bit 12 (received tar- get abort) in the PCI Status register. Figure 12 depicts a target abort cycle. ...

Page 110

... S5935 – PCI Product Figure 57. Target Abort Example PCI CLOCK (I) FRAME # (I) IRDY# (T) TRDY# (T) STOP# (T) DEVSEL# Figure 58. PCI Bus Arbitration and S5935 Bus Ownership Example 2 1 S5933 REQ# "OTHER" REQ# S5933 GNT# "OTHER" GNT# FRAME# ADDRESS AD[31:0] IRDY# TRDY# IDLE S5933 TRANSACTION 110 ...

Page 111

... FRAME# asserted). The S5935 also implements the PCI Master Latency Timer. Once granted the bus, the S5935 is guaranteed ownership for a minimum amount of time defined by the Master Latency Timer. The S5935 initiator, cannot control the responsiveness of a particular target nor the bus arbitration delay ...

Page 112

... S5935 – PCI Product Bus Acquisition Once GNT# is asserted, giving bus ownership to the S5935, the S5935 must wait until the PCI bus becomes idle. This delay is called bus acquisition latency and involves the state of the signals FRAME# and IRDY#. The current bus master must complete its current transaction before the S5935 may drive the bus ...

Page 113

... Figure 17. The S5935 responds to and supports bus masters which lock target. When the S5935 is a bus master, it never attempts to lock a target, but it honors a target’s request for retry if that target is locked by another master ...

Page 114

... PAR, PERR# and SERR#. The S5935 asserts SERR detects odd parity dur- ing an address phase, if enabled. The SERR# enable bit is bit 8 in the S5935 PCI Command Register. The odd parity error condition involves the state of signals AD[31:0] and C/BE[3:0]# when FRAME# is first asserted and the PAR signal during the following clock ...

Page 115

... S5935 – PCI Product Figure 63. Error Reporting Signals 12 PCI CLOCK (I) FRAME (I) ADDR A AD[31:0] (I) CMD AA C/BE[3:0]# (T) PAR SERR# (T) (T) PERR# READ TRANSACTION AMCC Confidential and Proprietary (T) (I) DATA A ADDR BB DATA BB CMD BE's BYTE ENABLES (I) GOOD A ERROR GOOD A ERROR A B WRITE TRANSACTION Revision 1.02 – ...

Page 116

... PCI bus and how they are accessed from the Add-On interface. ADD-ON OPERATION REGISTER ACCESSES The S5935 Add-On bus interface is very similar to that of a memory or peripheral device found in a micropro- cessor-based system. A 32-bit data bus with individual read and write strobes, a chip enable and byte enables are provided ...

Page 117

... For asynchronous writes (Figure 2), data is clocked into the S5935 on the rising edge of the WR# input. Address, byte enables, and data must all meet setup and hold times relative to the rising edge or WR#. WR# has both a minimum inactive time and a mini- mum active time for asynchronous accesses ...

Page 118

... S5935 – PCI Product Figure 64. Asynchronous Add-On Operation Register Read BE[3:0]# ADR[6:2] DQ[31:0] SELECT# RD# Figure 65. Asynchronous Add-On Operation Register Write BE[3:0]# ADR[6:2] DQ[31:0] SELECT# WR# 118 DS1527 Revision 1.02 – June 27, 2006 Valid Byte Enables Valid Address Valid Data Out Valid Byte Enables Valid Address Valid Data In ...

Page 119

... S5935 – PCI Product Figure 66. Synchronous FIFO or Pass-Thru Data Register Read BPCLK ADR[6:2] Valid 1 BE[3:0]# DQ[31:0] RD# RDFIFO# SELECT# Figure 67. Synchronous FIFO or Pass-Thru Data Register Write BPCLK ADR[6:2] Valid 1 BE[3:0]# DQ[31:0] Valid Data In 1 WR# WRFIFO# SELECT# AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 Valid 2 ...

Page 120

... ADR[6:2] and BE[3:0]# inputs are ignored when using the FIFO direct access inputs. RDF IF O# and WRFIFO# are useful for Add-On designs which cas- cade an external FIFO into the S5935 FIFO or use dedicated external logic to access the FIFO. Direct access signals always access the FIFO as 16- bits or 32-bits, whatever the MODE pin is configured for ...

Page 121

... S5935 data book shows the D31:29 bit combinations for reading, writing, and loading ad- dress/data information. Additionally, D31 doubles as an S5935 status bit. A ‘1’ indicates that the S5935 is currently busy reading or writing to the NVRAM. A ‘0’ indicates a complete or inactive state. ...

Page 122

... S5935 – PCI Product For the examples below, we will assume the S5935 is I/O mapped with a base address of FC00h. These This example will write 1 byte from NVRAM location 0040h and read it back: In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). ...

Page 123

... S5935 – PCI Product This example will read 1 byte from NVRAM location 0040h: In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). Out FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address latch ...

Page 124

... This is approximately 65 KHz (with a 33 MHz PCI clock). Any serial memory device that operates at this frequency is compatible with the S5935. For byte-wide accesses, the S5935 generates the waveforms shown in Figures 5 and 6. Figure 5 shows an nv memory read operation. Figure 6 shows an nv memory write operation. Read operations are always the same length ...

Page 125

... S5935 – PCI Product Memory Device Requirements for Write Accesses Timing Write cycle time Address valid to write active Data valid to write inactive Data hold from write inactive Write pulse width Write inactive Figure 69. nv Memory Write Operation EWR# (OUTPUT) EA[15:0] (OUTPUT) EQ[7:0] (OUTPUT) AMCC Confidential and Proprietary Spec ...

Page 126

... S5935 – PCI Product MAILBOX OVERVIEW The S5935 has eight 32-bit mailbox registers. The mailboxes are useful for passing command and status information between the Add-On and the PCI bus. The PCI interface has four incoming mailboxes (Add-On to PCI) and four outgoing mailboxes (PCI to Add-On). ...

Page 127

... PCI incoming mailbox 4, byte 3 (Add-On outgoing mailbox 4, byte 3) does not function exactly like the other mailbox bytes. When an a serial nv memory boot device or no external boot device is used, the S5935 pins EA7:0 are redefined to provide direct external access to Add-On outgoing mailbox 4, byte 3. EA8 is ...

Page 128

... PCI mailbox read completes (TRDY# deasserted). IRQ# is deasserted immediately when the Add-On clears the mailbox interrupt. When the S5935 is used with a serial nv memory boot device or no external boot device, the device pins EA8:0 are redefined. EA7:0 become EMB7:0 data inputs and EA8 becomes EMBCLK, a load clock ...

Page 129

... The MBEF and AMBEF are read- only. Status bits cannot cleared by writes to the status registers. The S5935 allows the mailbox status bits to be reset through software. The Bus Master Control/Status (MCSR) PCI Operation Register and the Add-On Gen- eral Control/Status (AGCSTS) Add-On Operation Register each have a bit to reset mailbox status ...

Page 130

... S5935 – PCI Product Mailbox operations for the Add-On interface are functionally identical. The following sequences are suggested for Add-On mailbox operations using status polling (interrupts disabled): Reading an Add-On Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the PCI interface. ...

Page 131

... The interrupt service routine tasks are shown below: Servicing a PCI mailbox interrupt (INTA#): 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). INTCSR ...

Page 132

... S5935 – PCI Product 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). AINT Bit 16 AINT Bit 17 2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written. ...

Page 133

... S5935 – PCI Product AMCC Confidential and Proprietary (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book DS1527 133 ...

Page 134

... BYTE 4-7 (NOTE1) NOTE 1: D24 AND D25 MUST BE ALSO "1" 134 DS1527 either a PCI target or program it to enable the S5935 PCI initiator (bus master). The following sec- tions describe functional level, the capabilities of the S5935 FIFO interface. FIFO Buffer Management and Endian Conversion The S5935 provides a high degree of flexibility for con- trolling the data flow through the FIFO ...

Page 135

... S5935 – PCI Product The configurable FIFO advance condition may be used to transfer data to and from Add-On interfaces which are not 32-bits wide. For a 16-bit Add-On bus, the Add-On to PCI FIFO advance condition can be set to byte 2. This allows a 16-bit write to the lower 16-bits ...

Page 136

... S5935 – PCI Product 64-Bit Endian Conversion Because the S5935 interfaces to a 32-bit PCI bus, special operation is required to handle 64-bit data endian con- version. Figure 2c shows 64-bit endian conversion. The S5935 must know whether the lower 32-bits enter the FIFO first or the upper 32-bits enter the FIFO first. INTCSR D31:30 identify which method is used by the applica- tion ...

Page 137

... Enable bus mastering for Add-On initiated 1 PCI writes 1. These signals are only available when a serial non-volatile mem- ory is used and the S5935 is configured for Add-On initiated bus mastering. PCI Bus Mastering with the FIFO The S5935 may initiate PCI bus cycles through the FIFO interface ...

Page 138

... S5935 defaults to PCI initiated bus mastering. Address and Transfer Count Registers The S5935 has two sets of registers used for bus mas- ter transfers. There are two operation registers for bus master read operations and two operation registers for bus master write operations ...

Page 139

... The Add-On to PCI FIFO status indi- cators change one PCI clock after a PCI read. For PCI writes to the PCI to Add-On, the S5935 asserts TRDY# and completes the PCI cycle (Figure 5). If the PCI bus attempts to write a full FIFO, the S5935 immediately issues a disconnect with retry (Fig- ure 6) ...

Page 140

... S5935 – PCI Product FIFO PCI Interface (Initiator Mode) The S5935 can act as an initiator on the PCI bus. This allows the device to gain control of the PCI bus to transfer data to or from the FIFO. Internal address and transfer count registers control the number of PCI transfers and the locations of the transfers ...

Page 141

... Figure 76. PCI Write to an Empty S5935 FIFO PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Add-on Signals RDEMPTY FRF Figure 77. PCI Write to a Full S5935 FIFO (Target Disconnect) PCI Signals PCI_CLK FRAME# AD[31:0] IRDY# TRDY# DEVSEL# STOP# Add-on Signals RDEMPTY FRF AMCC Confidential and Proprietary ...

Page 142

... PCI to Add-On FIFO. If the Add-On can empty the FIFO as quickly as it can be filled from the PCI bus, very long bursts are possible. The S5935 deasserts REQ# when it completes the access to fill the last location in the FIFO. Once REQ# is deas- serted, it will not be reasserted until the FIFO management condition is met ...

Page 143

... RDFIFO# is asserted, data 2 is presented on the DQ bus (as there was no BPCLK edge to advance the FIFO). A synchronous FIFO interface has the advantage of allowing data to be accessed more quickly (in bursts) by the Add-On target full S5935 FIFO is writ- Figure 78. Synchronous FIFO Register Burst Read Access Example BPCLK BE[3:0]# ADR[6:2] ...

Page 144

... Additional Status/Control Signals for Add-On Initi- ated Bus Mastering If a serial non-volatile memory is used to configure the S5935, and the device is configured for Add-On initi- ated bus mastering, two additional FIFO status signals and four additional control signals are available to the Add-On interface. The FRF and FWE outputs provide additional FIFO status information ...

Page 145

... BE3# becomes ADR1. With the FIFO direct access signals (RDFIFO# and WRFIFO#), the MODE pin must reflect the actual Add- On data bus width. With MODE = 16-bits, the S5935 automatically takes two consecutive, 16-bit Add-On writes to the FIFO and assembles a 32-bit value. FIFO reads operate in the same manner ...

Page 146

... FIFO operation. FIFO Setup During Initialization Location 45h in an external non-volatile memory may be used to configure the S5935 FIFO during initializa- tion external non-volatile memory is used, FIFO operation is disabled. The value of bit 7 in location 45h determines if the ...

Page 147

... Bit 8 Write vs. read priority 5. Define transfer source/destination These registers are written with the first address that accessed by the S5935. These address registers are updated after each access to indicate the next address to be accessed. Transfers must start on DWORD boundaries. MWAR All ...

Page 148

... AGCSTS Bit 26 Reset PCI to Add-On FIFO flags 4. Define FIFO management scheme. These bits define what FIFO condition must exist for the PCI bus request (REQ asserted by the S5935. This must be programmed through the PCI interface. MCSR Bit 13 PCI to Add-On FIFO management ...

Page 149

... Add-On interface may be selected, for use with a variety of Add-On memory or peripheral devices. Pass-Thru features can be used only when the S5935 is a PCI target target, the S5935 Pass-Thru mode supports single data transfers as well as burst transfers. When accessed with burst transfers, the S5935 supports data transfers at the full PCI band- width ...

Page 150

... Pass-Thru interface are implemented with a handshaking scheme. If the PCI bus writes to an S5935 Pass-Thru region, Add-On logic must read the data from the S5935 and store it on the Add-On. If the PCI bus reads from a Pass-Thru region, Add-On logic must write data to the S5935. ...

Page 151

... Add-On Pass-Thru status outputs are set to initiate a transfer on the Add-On side. If the Pass-Thru logic is currently busy completing a previ- ous access, the S5935 signals a retry to PCI initiator. The following sections describe the behavior of the PCI interface for Pass-Thru accesses to the S5935. ...

Page 152

... PCI specification allows 16 clocks to respond to the first data phase of a PCI cycle and 8 clocks for subsequent data phases (in the case of a burst) before a retry must be requested by the S5935. The S5935 also requests a retry if an initiator attempts to burst past the end of a Pass-Thru region. The ...

Page 153

... S5935 – PCI Product PCI Read Retries When the S5935 requests a retry for a PCI Pass-Thru read, it indicates that the Add-On could not complete the read in the required time. The Pass-Thru data can- not be read by the PCI interface until the Add-On asserts PTRDY#, indicating the access is complete. ...

Page 154

... S5935 – PCI Product The PCI bus cycle address information is stored in the S5935 Pass-Thru Address Register. Clock 0: The PCI address is recognized as a write to Pass-Thru region 1. The PCI data is stored in the S5935 Pass-Thru Clock 1: Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring. ...

Page 155

... BPCLK rising edge is required). The PCI bus cycle address is stored in the S5935 Pass-Thru Address Register. Clock 0: The PCI address is recognized as an access to Pass-Thru region 1. PCI data is stored in the S5935 Pass-Thru Clock 1: Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring. ...

Page 156

... PCI transfer, the S5935 stores the PCI address into the Pass-Thru Address Register (APTA). If the S5935 determines that the address is PCI address information is stored in the S5935 Pass-Thru Address Register. The PCI cycle is recognized as an Clock 0: access to Pass-Thru region 1. PTATN# is asserted by the S5935 to indicate a Pass-Thru access is occurring. ...

Page 157

... Clock 7: reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 8 to store DATA 4 from the S5935. PTRDY# asserted at the rising Clock 8: edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted again, causing PTATN deasserted ...

Page 158

... PCI system). In this example, the Add-On interface accepts data every other clock. In the example, RD# is asserted during the entire Add-On burst, but it can be deasserted when PTRDY# is deasserted, the S5935 functions the same under both conditions. Revision 1.02 – June 27, 2006 Data Book ...

Page 159

... S5935 – PCI Product Figure 84. Pass-Thru Burst Writes Controlled by PTRDY# AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 Data Book DS1527 159 ...

Page 160

... Clock 9: is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus. Add-On logic uses the rising edge of clock 10 to store DATA 4 from the S5935. PTRDY# asserted at the rising Clock 10: edge of clock 10 completes the current data phase. DATA 5 is driven on the Add-On bus. PTBURST# is deas- serted, indicating that on the PCI bus, the burst is complete except for the last data phase ...

Page 161

... AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 into the Pass-Thru Address Register (APTA). If the S5935 determines that the address is within one of its defined Pass-Thru regions, it indicates to the Add-On that a write to the Pass-Thru Data Register (APTD) is required. Figure 6 shows a 6 data phase Pass-Thru burst read access (Add-On write) using PTADR# ...

Page 162

... WR# asserted at the rising edge of clock 4 writes DATA 2 into the S5935. PTRDY# asserted at the rising edge Clock 4: of clock 4 completes the current data phase. WR# asserted at the rising edge of clock 5 writes DATA 3 into the S5935. PTRDY# asserted at the rising edge Clock 5: of clock 5 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN deasserted ...

Page 163

... Revision 1.02 – June 27, 2006 In this example, the Add-On interface writes data every other clock cycle. WR# is shown asserted during the entire Add-On burst, but WR# can be deasserted when PTRDY# is deasserted, the S5935 functions the same under both conditions. Data Book DS1527 163 ...

Page 164

... Add-On logic continues to drive DATA 4 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. WR# asserted at the rising edge of clock 9 writes DATA 4 into the S5935. PTRDY# asserted at the rising edge Clock 9: of clock 9 completes the current data phase. ...

Page 165

... AMCC Confidential and Proprietary phase of a PCI read operation. FRAME# is asserted during the rising edge of PCI clock 1. From this point, the S5935 has 16 clock cycles to respond to the initia- tor with TRDY# (completing the cycle). FRAME# could remain asserted, indicating a burst read, but the retry request conditions are identical for a single data phase read and the first data phase of a burst read ...

Page 166

... On logic must assert PTRDY# by the rising edge of BPCLK 8 to prevent the S5935 from asserting STOP#, requesting a retry. Meeting this condition allows the S5935 to assert TRDY# by the rising edge of PCICLK 8, completing the data phase with requiring a retry. When the S5935 requests a retry, the Pass-Thru sta- tus indicators remain valid (allowing the Add-On logic to complete the access) ...

Page 167

... The internal data bus is steered to the correct portion of APTD using the BE[3:0]# inputs. Table 1 shows the byte lane steering mechanism used by the S5935. The BYTEn symbols indicate data bytes in the Pass-Thru Data Register. When a read is performed with a BEn# input asserted, the corresponding PTBEn# output is deasserted. Add- AMCC Confidential and Proprietary Revision 1.02 – ...

Page 168

... S5935 – PCI Product Table 44. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write) Byte Enables Table 45. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read) Defined PT-Bus Width ...

Page 169

... This process continues until all bytes have been read from the APTD Register. During clock 5, RD# is deas- serted and PTRDY# is asserted. PTRDY# is sampled by the S5935 at the rising edge of clock 6, and the cur- rent data phase is completed. PTATN# is deasserted and new data can be written from the PCI bus. In this example, the byte enables are asserted, sequentially, from BE0# to BE3# ...

Page 170

... This operation limits each Pass-Thru region to a maximum size of 512 Mbytes of memory. For I/O mapped regions, the PCI specification allows no more than 256 bytes per region. The S5935 allows larger regions to be requested by the Add-On, but a PCI BIOS will not allocate the I/O space and will prob- ably disable the region ...

Page 171

... S5935 – PCI Product as ones. The number of zeros read back indicates the amount of memory or I/O space a particular S5935 Pass-Thru region is requesting. After the host reads all Base Address Registers in the system (as every PCI device implements from one to six), the PCI BIOS allocates memory and I/O space to each Base Address region ...

Page 172

... S5935 – PCI Product 172 DS1527 (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...

Page 173

... S5935 – PCI Product ABSOLUTE MAXIMUM RATINGS Parameter Storage Temperature Supply Voltage (VCC) Input Pin Voltage Power Dissipation DC CHARACTERISTICS The Following table summarizes the required parameters defined by the PCI specification as they apply to the S5935 controller. PCI Input/Output Electrical Characteristics Symbol Parameter ...

Page 174

... S5935 – PCI Product PCI BUS SIGNALS The following table summarizes the PCI Bus DC parameters defined by the PCI specification as they apply to the S5935 controller. Signal Type CLK RST# INTA# Open Drain AD[31:0] t/s REQ# t/s GNT# C/BE[3:0]# t/s DEVSEL# s/t/s FRAME# s/t/s IRDY# s/t/s TRDY# s/t/s PERR# s/t/s PAR t/s SERR# Open Drain ...

Page 175

... S5935 – PCI Product ADD-ON BUS SIGNALS Signal Type PCLK IRQ# SYSRST# ADR[6:2] SELECT ADR[6:2] BE[3:0]# RD# WR# DQ[31:0] t/s WRFULL RDEMPTY RDFIFO# WRFIFO# PTATN# PTBURST# PTADR# PTRDY# PTWR PTBE[3:0]# PTNUM[1:0] EQ[7:0] t/s EA[8:0] t/s EA[15:9] MODE TEST FLT# AMCC Confidential and Proprietary Direction Max Output 8 Output 4 Output 4 Input Input ...

Page 176

... S5935 – PCI Product Signal Type ERD#/SCL EWR#/SDA t/s AC CHARACTERISTICS PCI Bus Timings Functional Operation Range (V CC =5.0V ±5%, 0°C to 70° load on outputs) Symbol TCL Cycle Time t1 High Time t2 Low Time t3 Rise Time (0.8V to 2.0V) t4 Fall Time (2.0V to 0.8V) t5 Output Valid Delay (Bussed Signals) ...

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... S5935 – PCI Product Figure 92. PCI Output Timing PCI CLK OUTPUT DELAY TRI-STATE OUTPUT Figure 93. PCI Input Timing PCI CLK INPUT AMCC Confidential and Proprietary 1 1.5 1.5 1 Inputs Valid Revision 1.02 – June 27, 2006 Data Book t 9 DS1527 177 ...

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... S5935 – PCI Product ADD-ON BUS TIMINGS Figure 94. Add-On Clock Timing t 1 2.0 Figure 95. Pass-Thru Clock Relationship to PCI Clock PCI CLK BPCLK 178 DS1527 t 2.0 2.0 V IH2 0.8 0 TCL t 10 Revision 1.02 – June 27, 2006 Data Book 2.0 0.8 AMCC Confidential and Proprietary ...

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... S5935 – PCI Product Synchronous RDFIFO# Timing Functional Operation Range (VCC=5.0V 5 Ta’ loaf on outputs). Symbol t RDFIFO# Setup tp BPCLK Rising Edge 144 t RDFIFO# Low Time 145 t RDFIFO# Low to DQ[31:0] Driven 146 t RDFIFO# High to DQ[31:0] Float 148 t DQ[31:0] Valid from BPCLK Rising Edge ...

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... S5935 – PCI Product Synchronous WRFIFO# Timing Functional Operation Range (VCC= 5.0V 5 Ta’ load on outputs). Symbol t WRFIFO# Setup to BPCLK Rising Edge 150 t WRFIFO# Hold Time to BPCLK Rising Edge 150a t DQ[31:0] Setup to BPCLK Rising Edge 151 t DQ[31:0] Hold from BPCLK Rising Edge ...

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... S5935 – PCI Product Asynchronous RD# Register Access Timing Functional Operation Range (VCC=5.0V 5 Ta’ load on outputs). Symbol t SELECT# Setup to RD# Rising Edge 110 t SELECT# Hold from RD# Rising Edge 114a t ADR[6:2] Setup to RD# Rising Edge 114 t ADR[6:2] Hold from RD# Rising Edge ...

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... S5935 – PCI Product Asynchronous WR# Register Access Timing Functional Operation Range (VCC=5.0V 5 load on outputs). Symbol t SELECT# Setup to WR# Rising Edge 111 t SELECT# Hold from WR# Rising Edge 111a t ADR[6:2] Setup to WR# Rising Edge 115 t ADR[6:2] Hold from WR# Rising Edge ...

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... S5935 – PCI Product Synchronous RD# FIFO Timing Functional Operation Range (VCC=5.0V 5 load on outputs). Symbol t SELECT# Setup to BPCLK Rising Edge 112 t SELECT# Hold from BPCLK Rising Edge 112a t ADR[6:2] Setup to BPCLK Rising Edge 116 t ADR[6:2] Hold from BPCLK Rising Edge ...

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... S5935 – PCI Product Synchronous Multiple RD# FIFO Timing Figure 101. Synchronous RD# FIFO Timing 184 DS1527 Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...

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... S5935 – PCI Product Synchronous WR# FIFO Timing Functional Operation Range (VCC=5.0V 5 Ta’ load on outputs). Symbol t113 SELECT# Setup to BPCLK Rising Edge t113a SELECT# Hold from BPCLK Rising Edge t117 ADR[6:2] Setup to BPCLK Rising Edge t117a ADR[6:2] Hold from BPCLK Rising Edge ...

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... S5935 – PCI Product Synchronous Multiple WR# FIFO Timing Figure 103. Synchronous Multiple WR# FIFO Timing 186 DS1527 Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...

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... S5935 – PCI Product Target S5935 Pass-Thru Interface Timings Functional Operation Range (VCC=5.0V 5 load on outputs) Symbol t SELECT# Setup to BPCLK Rising Edge 10a t SELECT# Hold from BPCLK Rising Edge 11a t ADR[6:2], BE[3:0]# to Valid DQ [31: ADR[6:2], BE[3:0]# Setup to BPCLK Rising Edge ...

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... S5935 – PCI Product Figure 104. Pass-Thru Data Register Read Timing BPCLK t 13 ADR[6:2] Valid 1 BE[3:0 DQ[31: RD# SELECT# PTRDY# Figure 105. Pass-Thru Data Register Write Timing BPCLK t 13 ADR[6:2] Valid 1 BE[3:0 DQ[31:0] Valid Data WR# SELECT# t 10a PTRDY# 188 ...

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... S5935 – PCI Product Figure 106. Pass-Thru Status Indicator Timing BPCLK PTATN# PTWR PTBURST# PTNUM[1:0] PTBE[3:0]# Target Byte-Wide nv Memory Interface Timings Functional Operation Range (V CC =5.0V ±5%, 0°C to 70° load on outputs) Symbol t ERD# Cycle Time 35 t ERD# Low Time 36 t ERD# High Time ...

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... S5935 – PCI Product Figure 107. nv Memory Read Timing ERD# (OUTPUT) t EA[15:0] (OUTPUT) EQ[7:0] (INPUT) Figure 108. nv Memory Write Timing EWR# (OUTPUT) EA[15:0] (OUTPUT) EQ[7:0] (OUTPUT) 190 DS1527 Address Valid Address Valid t 45 Data Valid Revision 1.02 – June 27, 2006 Data Book ...

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... S5935 – PCI Product Target Interrupt Timings Functional Operation Range (V CC =5.0V ±5%, 0°C to 70° load on outputs) Symbol t IRQ# Low from BPCLK Rising Edge 49 t IRQ# High from BPCLK Rising Edge 50 Notes: 1. This timing applies to interrupts generated and cleared from the PCI interface. ...

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... S5935 – PCI Product 192 DS1527 (This page intentionally left blank.) Revision 1.02 – June 27, 2006 Data Book AMCC Confidential and Proprietary ...

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... S5935 – PCI Product S5935 Pinout and Pin Assignment - 160 PQFP EA10 121 122 PTNUM1 PTNUM0 123 IRQ# 124 DQ19 125 SYSRST# 126 EWR#/SDA 127 ERD#/SCL 128 EA11 129 VSS 130 VCC 131 ADR6 132 DQ18 133 NC 134 135 ...

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... S5935 – PCI Product S5935 Pinout and Pin Assignment - 208 TQFP VDD 157 VSS 158 VSS 159 EA10 160 PTNUM1 161 PTNUM0 162 IRQ# 163 DQ19 164 STSRST# 165 SDA/EWR 166 SCL/ERD 167 N/C 168 EA11 169 VSS 170 171 VSS VDD ...

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... S5935 – PCI Product S5935 Numerical Pin Assign- ment - 160 PQFP Pin# Signal Type 1 EQ0 t/s 2 AD23 t/s 3 AD22 t/s 4 AD21 t/s 5 DQ31 t/s 6 AD20 t/s 7 AD19 t/s 8 AD18 t/s 9 EQ1 t/s 10 VSS V 11 VCC V 12 AD17 t/s 13 DQ30 t/s 14 AD16 t/s 15 C/BE2# t/s 16 FRAME# t/s 17 EQ2 t/s 18 IRDY# t/s 19 TRDY# t/s 20 DEVSEL# t/s 21 EQ3 t/s 22 STOP# t/s 23 LOCK PERR# ...

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... S5935 – PCI Product Pin# Signal Type 98 DQ2 t/s 99 DQ1 t/s 100 DQ0 t/s 101 EA7 t/s 102 WRFIFO# in 103 WRFULL out 104 RDFIFO# in 105 DQ21 t/s 106 RDEMPTY out 107 PTADR# in 108 PTWR out 109 EA8 t/s 110 VSS V 111 VCC V 112 PTBURST# out 113 EA9 ...

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... S5935 – PCI Product Package Physical Dimensions - 160 PQFP Figure 111. S5935 - 160 PQFP Package Drawing PACKAGE MATERIAL NOTE: Green/RoHS Compliant Package: Lead Finish - MATTE SN. AMCC Confidential and Proprietary Revision 1.02 – June 27, 2006 Data Book DS1527 197 ...

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... S5935 – PCI Product Figure 112. S5935 - Marking Drawing LEGEND (in row order - including symbols): ROW #1: AMCC Logo (fixed) ROW #2: AMCC Device Part Number (fixed) ROW #3: S5935: Core Part Number (fixed) UUU: Ordering Options (eg. package identifier, lead free, speed grade, ...). Character Length may vary Depending on Options Selected ...

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... S5935 – PCI Product S5935 Numerical Pin Assign- ment - 208 TQFP Pin# Signal Type 1 VDD V 2 VSS V 3 VSS V 4 EQ0 t/s 5 AD23 t/s 6 AD22 t/s 7 AD21 t/s 8 DQ31 t/s 9 AD20 t/s 10 AD19 t/s 11 AD18 t/s 12 N/C --- 13 EQ1 t/s 14 VSS V 15 VSS V 16 VDD V 17 VDD V 18 AD17 t/s 19 DQ30 t/s 20 AD16 ...

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... S5935 – PCI Product Pin# Signal Type 98 DQ24 t/s 99 VSS V 100 DQ14 t/s 101 DQ13 t/s 102 DQ12 t/s 103 VDD V 104 VDD V 105 VDD V 106 VSS V 107 VSS V 108 EA4 t/s 109 DQ11 t/s 110 DQ10 t/s 111 DQ9 t/s 112 DQ23 t/s 113 DQ8 t/s 114 BE0 I 115 DQ7 ...

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