SC16C554 Philips Semiconductors, SC16C554 Datasheet

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SC16C554

Manufacturer Part Number
SC16C554
Description
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Manufacturer
Philips Semiconductors
Datasheet

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1. Description
2. Features
The SC16C554/554D is a 4-channel Universal Asynchronous Receiver and
Transmitter (QUART) used for serial data communications. Its principal function is to
convert parallel data into serial data and vice versa. The UART can handle serial data
rates up to 5 Mbit/s. It comes with an Intel or Motorola interface.
The SC16C554/554D is pin compatible with the ST16C554 and TL16C554 and it will
power-up to be functionally equivalent to the 16C454. Programming of control
registers enables the added features of the SC16C554/554D. Some of these added
features are the 16-byte receive and transmit FIFOs, automatic hardware or software
flow control and Infrared encoding/decoding. The selectable auto-flow control feature
significantly reduces software overload and increases system efficiency while in FIFO
mode by automatically controlling serial data flow using RTS output and CTS input
signals. The SC16C554/554D also provides DMA mode data transfers through FIFO
trigger levels and the TXRDY and RXRDY signals. On-board status registers provide
the user with error indications, operational status, and modem interface control.
System interrupts may be tailored to meet user requirements. An internal loop-back
capability allows on-board diagnostics.
The SC16C554/554D operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages.
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA)
encoder/decoder
Rev. 05 — 10 May 2004
5 V, 3.3 V and 2.5 V operation
Industrial temperature range
The SC16C554/554D is pin compatible with the industry-standard
ST16C454/554, ST68C454/554, ST16C554, TL16C554
Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
16-byte transmit FIFO
16-byte receive FIFO with error flags
Automatic software/hardware flow control
Programmable Xon/Xoff characters
Software selectable Baud Rate Generator
Four selectable Receive FIFO interrupt trigger levels
Standard modem interface or infrared IrDA encoder/decoder interface
Sleep mode
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Product data

Related parts for SC16C554

SC16C554 Summary of contents

Page 1

... System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C554/554D operates 3.3 V and 2.5 V, and the industrial temperature range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages. 2. Features ...

Page 2

... Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder 8-bit characters Even, Odd, or No-Parity formats 2-stop bit 2 Baud generation ( Mbit/s) Loop-back controls for communications link fault isolation Rev. 05 — 10 May 2004 SC16C554/554D Version SOT188-2 10 1.4 mm SOT314-2 10 1.4 mm SOT314 ...

Page 3

... A0–A2 REGISTER CSA-CSD SELECT LOGIC 16/68 INTA-INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC INTSEL Fig 1. SC16C554/554D block diagram (16 mode). 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder TRANSMIT FIFO REGISTERS FLOW CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW ...

Page 4

... CONTROL LOGIC A0–A4 REGISTER CS SELECT LOGIC 16/68 IRQ INTERRUPT TXRDY CONTROL RXRDY LOGIC Fig 2. SC16C554/554D block diagram (68 mode). 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder TRANSMIT FIFO REGISTERS FLOW CONTROL LOGIC RECEIVE FIFO REGISTERS FLOW ...

Page 5

... RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 Fig 3. PLCC68 pin configuration (16 mode). 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder SC16C554DIA68 16 MODE Rev. 05 — 10 May 2004 SC16C554/554D 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD 55 INTD 54 CSD 53 TXD 52 IOR ...

Page 6

... RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 Fig 4. PLCC68 pin configuration (68 mode). 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder SC16C554DIA68 68 MODE Rev. 05 — 10 May 2004 SC16C554/554D 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD 55 n.c. 54 n.c. 53 TXD 52 n.c. 51 ...

Page 7

... CSB 11 INTB 12 RTSB 13 GND 14 DTRB 15 CTSB 16 Fig 5. LQFP64 pin configuration. 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder SC16C554IB64 SC16C554DIB64 Rev. 05 — 10 May 2004 SC16C554/554D 48 DSRD 47 CTSD 46 DTRD 45 GND 44 RTSD 43 INTD 42 CSD 41 TXD 40 IOR ...

Page 8

... GND 16 RXA 17 RIA 18 CDA 19 n.c. 20 Fig 6. LQFP80 pin configuration. 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder SC16C554IB80 Rev. 05 — 10 May 2004 SC16C554/554D 60 n.c. 59 CDC 58 RIC 57 RXC 56 GND 55 TXRDY 54 RXRDY 53 RESET 52 n.c. 51 ...

Page 9

... UART channels A through D. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C554/554D. Status can be tested by reading MSR[4]. This pin only affects the transmit or receive operations when Auto CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware fl ...

Page 10

... Data Terminal Ready (Active-LOW). These outputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the SC16C554/554D is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’ ...

Page 11

... Reset. In the 16 mode, a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See “SC16C554/554D external reset conditions” When 16/ logic 0 (68 mode), this pin functions similarly, but as an inverted reset interface signal, RESET. ...

Page 12

... Description I Receive data input RXA-RXD. These inputs are associated with individual serial channel data to the SC16C554/554D. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input internally. ...

Page 13

... SC16C554/554DAI68 is downward compatible with the 16C454/554 or the 68C454/554, dependent on the state of the interface mode selection pin, 16/68. The SC16C554/554D is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and Mbit/s with an external clock input (at 3.3 V and 2.5 V the maximum speed is 3 Mbit/s). ...

Page 14

... The 68 mode configures the package interface pins for connection with Motorola, and other popular microprocessor bus types. The interface operates similar to the 68C454/554. In this mode, the SC16C554/554D decodes two additional addresses, A3-A4, to select one of the four UART ports. The A3-A4 address decode function is ...

Page 15

... FIFO operation The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. With SC16C554 devices, the user can set the receive trigger level, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached ...

Page 16

... IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will be activated. Following a suspension due to a match of the Xoff characters’ values, the SC16C554/554D will monitor the receive data stream for a match to the Xon1,2 character value(s match is found, the SC16C554/554D will resume operation and clear the fl ...

Page 17

... EFR[0-3]. Note that software flow control should be turned off when using this special mode by setting EFR[0- logic 0. The SC16C554/554D compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to indicate detection of a special character ...

Page 18

... TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock MHz (for 3.3 V and 5 V operation), as required for supporting a 5 Mbit/s data rate. The SC16C554/554D can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/22-33 pF load) is ...

Page 19

... RX, RI, CTS, DSR, CD transmit data is provided by the user. If the sleep mode is enabled and the SC16C554/554D is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user ...

Page 20

... SHIFT FIFO REGISTER REGISTERS FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 05 — 10 May 2004 SC16C554/554D TXA-TXD IR ENCODER RXA-RXD IR DECODER RTSA-RTSD CTSA-CTSD DTRA-DTRD DSRA-DSRD OP1A-OP1D RIA-RID OP2A-OP2D CDA-CDD 002aaa170 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 21

... SHIFT FIFO REGISTER REGISTERS FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 Rev. 05 — 10 May 2004 SC16C554/554D TXA-TXD IR ENCODER RXA-RXD IR DECODER RTSA-RTSD CTSA-CTSD DTRA-DTRD DSRA-DSRD OP1A-OP1D RIA-RID OP2A-OP2D CDA-CDD 002aaa700 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 22

... Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder details the assigned bit functions for the SC16C554/554D internal registers. Bit 7 Bit 6 Bit 5 Bit 4 ...

Page 23

... FIFO full; logic least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C554/554D and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...

Page 24

... FIFO reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C554/554D in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). • ...

Page 25

... Logic 0 = Set DMA mode ‘0’ (normal default condition). Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C554/554D is in the 16C450 mode (FIFOs disabled; FCR[0] = logic the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0 ...

Page 26

... FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C554/554D is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. ...

Page 27

... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C554/554D provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...

Page 28

... Logic 0 or cleared = default condition. LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Logic 0 or cleared = default condition. Rev. 05 — 10 May 2004 SC16C554/554D Table 15). Table 16). Table 17). ...

Page 29

... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 05 — 10 May 2004 SC16C554/554D © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 30

... MCR[4] Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C554/554D I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...

Page 31

... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C554/554D and the CPU. Table 19: Bit 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Line Status Register bits description ...

Page 32

... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C554/554D has changed from a logic logic 1. A modem Status Interrupt will be generated. Rev. 05 — 10 May 2004 SC16C554/554D …continued © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 33

... Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C554/554D provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. ...

Page 34

... EFR[5] Special Character Detect. Logic 0 = Special character detect disabled (normal default condition). Logic 1 = Special character detect enabled. The SC16C554/554D compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...

Page 35

... Philips Semiconductors 7.11 SC16C554/554D external reset conditions Table 23: Register IER ISR LCR MCR LSR MSR FCR EFR Table 24: Output TXA, TXB, TXC, TXD RTSA, RTSB, RTSC, RTSD DTRA, DTRB, DTRC, DTRD RXRDY TXRDY 8. Limiting values Table 25: In accordance with the Absolute Maximum Rating System (IEC 60134). ...

Page 36

Table 26: DC electrical characteristics + 2 5.0 V 10%, unless otherwise specified. amb CC Symbol ...

Page 37

... Rev. 05 — 10 May 2004 SC16C554/554D 3.3 V 5.0 V Unit Min Max Min Max MHz ...

Page 38

... Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder …continued 10%, unless otherwise specified. Conditions 2.5 V Min Max [ 200 - 30h t 30w t 30d t 31h Rev. 05 — 10 May 2004 SC16C554/554D 3.3 V 5.0 V Min Max Min Max ...

Page 39

... Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder t t 30w 30h t 32h t 33h t 33s t 6h VALID ADDRESS t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA Rev. 05 — 10 May 2004 SC16C554/554D t 32d 002aaa211 002aaa171 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 40

... ACTIVE t 12h t 12d DATA t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE ACTIVE Rev. 05 — 10 May 2004 SC16C554/554D 002aaa172 CHANGE OF STATE t 18d ACTIVE ACTIVE t 19d ACTIVE ACTIVE t 18d CHANGE OF STATE 002aaa352 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 41

... Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 05 — 10 May 2004 SC16C554/554D 002aaa112 NEXT DATA PARITY STOP START BIT BIT BIT 20d ACTIVE t 21d ...

Page 42

... Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder DATA BITS (5– DATA BITS (5– Rev. 05 — 10 May 2004 SC16C554/554D NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY t ...

Page 43

... DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 05 — 10 May 2004 SC16C554/554D NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 44

... Philips Semiconductors Fig 20. Transmit ready timing in non-FIFO mode. 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder Rev. 05 — 10 May 2004 SC16C554/554D © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 45

... Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 05 — 10 May 2004 SC16C554/554D PARITY STOP BIT BIT D6 D7 002aaa346 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 46

... Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder UART FRAME DATA BITS BIT TIME RX BIT TIME Rev. 05 — 10 May 2004 SC16C554/554D 1/2 BIT TIME 3/16 BIT TIME 002aaa212 0-1 16X CLOCK DELAY DATA BITS UART FRAME 002aaa213 © ...

Page 47

... 24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07 0.958 0.958 0.93 0.93 0.995 0.995 0.048 0.05 0.950 0.950 0.89 0.89 0.985 0.985 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 05 — 10 May 2004 SC16C554/554D SOT188 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1. ...

Page 48

... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 1 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 05 — 10 May 2004 SC16C554/554D SOT314 detail X (1) ( 0.75 1.45 1.45 7 0.2 0.12 0.1 o 0.45 1.05 1.05 0 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © ...

Page 49

... scale (1) ( 0.18 12.1 12.1 14.15 14.15 0.5 1 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 05 — 10 May 2004 SC16C554/554D SOT315 detail X (1) ( 0.75 1.45 1.45 7 0.2 0.15 0.1 o 0.30 1.05 1.05 0 EUROPEAN ISSUE DATE PROJECTION ...

Page 50

... Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder 2.5 mm Rev. 05 — 10 May 2004 SC16C554/554D 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...

Page 51

... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, USON, VFBGA , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 05 — 10 May 2004 SC16C554/554D Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5][6] not recommended suitable ...

Page 52

... Hot bar soldering or manual soldering is suitable for PMFP packages. 9397 750 13132 Product data Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder 10 C measured in the atmosphere of the reflow Rev. 05 — 10 May 2004 SC16C554/554D © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 53

... RTS, DTR, OP2 and OP1.” Figure 8 and Figure 9 modified: signals to/from Modem Control Logic block corrected. description”: description of bit 2, IER[2], modified. description”: description of bit 6, EFR[6], and of Rev. 05 — 10 May 2004 SC16C554/554D © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 54

... Rev. 05 — 10 May 2004 SC16C554/554D Fax: + 24825 © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...

Page 55

... Modem Control Register (MCR 7.7 Line Status Register (LSR 7.8 Modem Status Register (MSR 7.9 Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C554/554D external reset conditions Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 37 10.1 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 38 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 47 © Koninklijke Philips Electronics N.V. 2004. ...

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