SC28C94 Philips Semiconductors, SC28C94 Datasheet

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... SC28C94 Quad universal asynchronous receiver/transmitter (QUART) Product specification Replaces SC26C94 of 1995 May 01 and SC68C94 of 1995 May 01 IC17 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1998 Aug 19 ...

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... Dog” timer for each receiver INDUSTRIAL V = +5V +10 – + SC28C94A1N SC28C94A1A 2 Product specification SC28C94 DACKN IACKN RQN I/O0a–d I/O1a–d I/O2a–d I/O3a–d TDa-d SD00158 DWG # G SOT240-1 SOT238-3 853–2111 19896 ...

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... I/O2A 16 I/O3B I/O0B 17 D1 I/O1B 18 D0 I/O2B 19 RXDA TXDA TXDA 20 RXDA Figure 2. Pin Configurations (cont Product specification SC28C94 IRQN 45 RXDD 44 43 TXDD 42 X1/CLK I/O3D RESET 38 TXDC 37 RXDC 36 ...

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... SS2 ISR V SS3 V SS4 1998 Aug 19 INTERNAL DATA BUS DUART AB 8 TIMING CONTROL 18 Figure 3. Block Diagram 4 Product specification SC28C94 CHANNEL A 8 BYTE TRANSMIT FIFO TxDA TRANSMIT SHIFT REGISTER 8 BYTE RECEIVE FIFO RxDA RECEIVE SHIFT REGISTER CSR Rx CSR Tx TxDB ...

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... X1, this pin should be left unconnected Power and grounds: respectively BUS INTERFACE A0-A5 D (7:0) DTACKN IACKN 1998 Aug 19 NAME AND FUNCTION BLOCK A COUNTER/TIMER BAUD I/O PORT CONTROL RATE GENERATOR UARTS A/B INTERRUPT CONTROL BLOCK B UARTS C/D I/O CONTROL I/O PORT CONTROL Figure 4. Channel Architecture 5 Product specification SC28C94 SD00161 ...

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... Enable DACKN Reserved Interrupt Vector Register (IVR) Update CIR Global Transmit Holding Reg (GTxFIFO) Interrupt Control Register (ICR) BRG Rate low high (use when Mhz) 2 Set X1/CLK divide by two 2 Set X1/CLK Normal Reserved Test Mode Reserved 6 Product specification SC28C94 ...

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... The value of D(7:0) is ignored. The START command always loads the contents of CTUR, CTLR to the counting registers. The STOP command always resets the ISR(3) bit in the interrupt status register. 7 Product specification SC28C94 ...

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... The break is terminated by a STOP BREAK command or a transmitter reset.. TxFIFO The TxFIFO empty positions are encoded as a three bit number for presentation to the bidding logic. The coding will equal the number of bytes that remain to be filled. That is, a binary number of 101 will 8 Product specification SC28C94 ...

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... In this mode of operation a ‘master’ station transmits an address character to the several ‘slave’ stations on the line. The address character is identified by setting its parity bit to 1. The slave stations will usually have their receivers partially enabled as a result of 9 Product specification SC28C94 ...

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... The channel number and interrupt type fields are hardwired. During the “bid arbitration” process all bids from enabled sources are presented, simultaneously internal interrupt bus. The bidding system and formats are discussed in more detail in following sections. 10 Product specification SC28C94 ...

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... The buffers driving the CIR to the DBUS also provide the means of implementing the Global Interrupting Channel and Global Byte Count Registers, described in a later section. The winning bid channel number and interrupt type fields can also be used to generate part of the Interrupt Vector, as defined by the Interrupt Control Register. 11 Product specification SC28C94 ...

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... The operation of the QUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. Addressing of the registers is described in Table 1. The bit formats of the QUART registers are depicted in Table 2. 12 Product specification SC28C94 Chan # 2 Chan # 2 SD00163 ...

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... Yes 1 = Yes Overrun Error TxEMT Yes 1 = Yes Delta I/O1b 0 = off Product specification SC28C94 Bit 1 Bit 0 These bits not implemented Parity Type Bits per Character Stop Bit Length* Transmitter Clock Select See text ...

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... FIFO. In the block mode, the status provided in the SR for these bits is the accumulation (logical-OR) of the status for all characters coming to the top of the FIFO since the last reset error command was issued. 14 Product specification SC28C94 Bit 1 Bit 0 RxRDY/ TxRDYa FFULLa ...

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... If an external 1X clock is used for the transmitter, MR2[ selects one stop bit and MR2[ selects two stop bits to be transmitted. RECEIVER NOTE: In all cases, the receiver only checks for a “mark” condition at the center of the stop bit (1/2 to 9/16 bit 15 Product specification SC28C94 ...

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... RxFIFO area are still available. Disable is not the same as a “receiver reset”. With a receiver reset any characters not read are lost. The command has no effect on the receiver status bits or any 16 Product specification SC28C94 ACR[ I/O3x – 16X I/O3x – 1X ...

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... FIFO to be read by the CPU set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the RxFIFO, and no more characters are in the FIFO. 17 Product specification SC28C94 TEST ACR[ ACR[ 4,800 7,200 ...

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... It does not mean it is generating an interrupt. ISR[3] – Counter Ready In the counter mode of operation, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command initialized to ‘0’ when the chip is reset. 18 Product specification SC28C94 ...

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... A change on the pin will be required to be stable for at least 26.04 s and as much as 52.08 s for the COS detectors to confirm a change. Note that changes in the X1/clock frequency will effect this stability requirement. COS detectors are reset by a read of the IPCR. 19 Product specification SC28C94 ...

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... I/O1A IPR(4), RxC in IPR(1), C/Tab Clk in OPRab(4) OPRab( RTSN if IOPCR[5: RTSN if IOPCR[5:4] RxC 1x RxC 16x RxC 16x RxC 1x 20 Product specification SC28C94 Bit 1 Bit 0 I/O1a I/O0a 0 = Low 0 = Low 1 = High 1 = High I/O1c I/O0c 0 = Low 0 = Low 1 = High 1 = High I/O0x CONTROL I/O1c I/O0c ...

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... Change of State x10 Transmit available 011 Receive available, no error 100 Receiver break change Chan # 101 Counter/Timer 111 Receive available, w/errors 2 21 Product specification SC28C94 IOPCRb[1:0] I/O0B IPR(2), CTSN OPRab(2) 01 TxC 1x TxC 16x IOPCRc[1:0] I/O0C 1 TxC in IPR(0), CTSN OPRcd(0) 01 TxC 1x TxC 16x ...

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... Holds the constant bits of the interrupt acknowledge vector. As shown, the three MSBs are always used, while the less significant bits can be replaced by the interrupt type code and/or Channel code bits contained in the CIR. The IVR is write only at address 29H. 22 Product specification SC28C94 IVC 6 2 State Change C/T ...

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... GND open open –140 – – CMOS input levels with X1 = 4MHz 23 Product specification SC28C94 UNIT UNIT Max 0 0 140 ...

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... PARAMETER PARAMETER With respect to a 3.6864MHz clock on pin X1/CLK 2 active) = 50pF 2. Test conditions for rest of outputs minimum test rate is 2.0MHz. CLK 24 Product specification SC28C94 LIMITS UNIT UNIT Min Typ Max 200 ...

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... CEN 3 RDN WRN 6 D[7:0] Figure 5. A Read Cycle Followed by a Write Cycle without DACKN 1998 Aug 19 1 CHARACTERISTIC CHARACTERISTIC READ CYCLE Product specification SC28C94 LIMITS UNIT UNIT Min Typ Max ...

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... CHARACTERISTIC 50pF, forced current for V = 4.0mA; forced current for READ CYCLE Product specification SC28C94 LIMITS UNIT UNIT Min Typ Max 110/115 90/122 + edges X1 edges 150 ...

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... NOTE: Rise time of IRQN is dependent on external circuit. OSC/N EVAL/HOLD IACKN CIR 1998 Aug 19 X1 edges 5 2 Figure 7. Interrupt Knowledge (IACKN) Timing VALUE FOR THIS INTERRUPT Figure 8. Interrupt Bid Arbitration Timing 27 Product specification SC28C94 LIMITS UNIT UNIT Min Typ Max ...

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... INTRAN–INTRDN, I/O0a–I/O3d D0–D7, TxDa–TxDh, I/O0a–I/O3d 1998 Aug 19 INTBUSN7:0 INVERTING LATCHES INTERRUPT TYPE Figure 9. Current Interrupt Register Logic 2.7K 60pF 6K 150pF Figure 10. AC Test Conditions on Outputs 28 Product specification SC28C94 CURRENT CHANNEL INTERRUPT REGISTER D0 SD00167 +5V +5V 1.6K SD00168 ...

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... Aug 19 t RES Figure 11. Reset Timing OLD DATA Figure 12. I/O Port Timing POINT 0.5V ABOVE V . THIS POINT REPRESENTS NOISE MARGIN THAT AS Figure 13. Interrupt Timing 29 Product specification SC28C94 SD00169 NEW DATA SD00170 V +0. +0. SD00171 ...

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... TYPICAL CRYSTAL SPECIFICATION FREQUENCY: LOAD CAPACITANCE (C L TYPE OF OPERATION: Figure 14. Clock Timing 1 BIT TIME ( CLOCKS t TXD t TCS Figure 15. Transmit Clock Timing 30 Product specification SC28C94 +5V 1K required for TTL gate STANDARD BRG BAUD RATES 38.4kHz CLOCK TO I/O CHANGE-OF-STATE DETECTORS To ...

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... CR[7:4] = 1010 NOTES: 1. TIMING SHOWN FOR MR2[ TIMING SHOWN FOR MR2[ 1998 Aug RXS RXH Figure 16. Receive Clock Timing D2 D3 BREAK D3 START D4 STOP BREAK BREAK Figure 17. Transmitter Data Timing 31 Product specification SC28C94 SD00174 WILL D6 NOT BE TRANSMITTED CR[7:4] = 1010 SD00175 ...

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... Figure 18. Receiver Data Timing BIT MR1 [ ADD#2 BIT 9 BIT STATUS DATA ADD#1 D0 Figure 19. Wake-Up Mode 32 Product specification SC28C94 D11 D12 D13 D10 RESET BY COMMAND D10 WILL BE OVERWRITTEN BY D11, 12, ETC SD00176 BIT 9 ADD#2 1 BIT 9 ...

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... Note that interrupt threshold value in the ICR is 6 bits long. This value is aligned with the bid arbitration logic such that it bids only 33 Product specification SC28C94 FUNCTION Receiver bid With error Receiver bid No error Transmit bid Receive Break ...

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... During a read of the QUART DACKN signals that valid data is on the data bus. During a write to the QUART DACKN signals that data placed on the bus by the control processor has been written to the 34 Product specification SC28C94 BIT 2 BIT 1 BIT 0 ICR[1:0] Channel number ...

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... QUART) The principles to keep in mind are: 1. When IACKN is not used the CIR should be updated via command DACKN is not used it should be disabled. 3. When in the asynchronous mode be sure DACKN is enabled. 4. With 68xxx type controllers the RDN signal must be generated. 35 Product specification SC28C94 ...

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... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) DIP48: plastic dual in-line package; 48 leads (600 mil) 1998 Aug 19 36 Product specification SC28C94 SOT240-1 ...

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... Philips Semiconductors Quad universal asynchronous receiver/transmitter (QUART) PLCC52: plastic leaded chip carrier; 52 leads; pedestal 1998 Aug 19 37 Product specification SC28C94 SOT238-3 ...

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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors 1998 Aug 19 [1] Copyright Philips Electronics North America Corporation 1998 Document order number: 38 Product specification SC28C94 All rights reserved. Printed in U.S.A. Date of release: 08-98 9397 750 04353 ...