SC28L202 Philips Semiconductors, SC28L202 Datasheet
SC28L202
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SC28L202 Summary of contents
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... SC28L202 Dual universal asynchronous receiver/transmitter (DUART) Objective specification Supersedes data of 2000 Jan 31 IC19 Data Handbook INTEGRATED CIRCUITS 2000 Feb 10 ...
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... Objective specification SC28L202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Objective specification SC28L202 25 25 ...
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... Objective specification SC28L202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Objective specification SC28L202 ...
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... Table 2. SC28L202 REGISTER BIT DESCRIPTIONS Table 3. ...
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... Automatic wake–up mode for multi–drop applications Start–end break interrupt/status Detects break which originates in the middle of a character On–chip crystal oscillator Power down mode at less than 10 a Receiver time–out mode Single +3.3V or +5V power supply 1 Objective specification SC28L202 rate) ...
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... Philips Semiconductors Dual UART ORDERING INFORMATION D Description i ti (Preliminary as of 1/31/00) (Preliminary as of 1/31/00) 52-Pin Plastic Quad Flat Pack (PQFP) 56-pin TSSOP 2000 Feb 10 Industrial V = +3.3 +5V 10 – +85 C amb SC28L202A1B SC28L202A1D 2 Objective specification SC28L202 D Drawing i Number Number SOT379-1 SOT364-1 ...
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... When these pins are configured for interrupt type signals (RxRDY, TxRDY, C/TRDY) They switch to open drain outputs. Vcc Power Power Supply: +3.3 or +5V supply input parameters are specified with respect to the Vcc being at 3.3 of 5.0 volts +/– 10% GND Power Ground (5 pins) 2000 Feb 10 (PRELIMINARY 2/10/00) 10% (4 pins). Operation is assured from 2.97 to 5.5 volts. Timing 3 Objective specification SC28L202 ...
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... They switch to open drain outputs Vcc Power Power Supply: +3.3 or +5V supply input parameters are specified with respect to the Vcc being at 3.3 of 5.0 volts +/– 10% Vss Power Ground (5 Vss Pins) 2000 Feb 10 10% (4 Vcc Pins) ). Operation is assured from 2.97 to 5.5 volts. Timing 4 Objective specification SC28L202 ...
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... Vcc Vss 16 Vss RxDB IACKN 27 Vcc 28 Vss 5 Objective specification SC28L202 Pin Function 29 CEN 30 RWN 31 DACKN 32 TxDB 33 I/O7B 34 I/O6B 35 I/O5B I/O4B 37 I/O3B 38 I/O2B 39 I/O1B 40 I/O0B 41 Vcc 42 Vcc 43 Vss 44 Vss 45 I/O7A 46 ...
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... Pin Function Pin Function Objective specification SC28L202 68xxx 52 Pin PQFP RxDA 27 I/O5B RESETN 28 I/O4B D7 29 I/O3B D6 30 I/O2B D5 31 I/O1B D4 32 I/O0B Vcc 33 Vcc Vss 34 Vss D3 35 I/O7A ...
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... I/O ports The SC28L202 is provided with 16 I/O ports. These ports are true input and/or output structures and are equipped with a change of state detector. The input circuit of these pins is always active. Under program control the ports my display internal signals or static logic levels ...
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... Use of different frequencies will change the “standard” baud rates by precisely the ratio of 14.7456 MHz to the different crystal frequency. An external clock MHz frequency range may be connected to X1/Sclk pin external clock is used instead of a crystal, X1/Sclk must be driven and X2 left floating or driving a load of not 8 Objective specification SC28L202 ...
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... The two PBRG Timers are programmable 16 bit dividers that are used for generating miscellaneous clocks. These clocks may be used by any or all of the receivers and transmitters in the SC28L202 or output to the general purpose I/O pins. Each timer unit has eight different clock sources available described in the PBRG clock source Register ...
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... Characters cannot be loaded into the TxFIFO while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit 10 Objective specification SC28L202 ...
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... The ”received break” will always be associated with a zero byte in the RxFIFO. It means that zero character was a break character and not a zero data byte. The reception of a break condition will always set the ”change of break” (see below) status bit in the Interrupt Status Register (ISR). 11 Objective specification SC28L202 ...
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... FIFO size) characters earlier. In either mode, reading the SR does not affect the RxFIFO. The RxFIFO address is advanced only when the RxFIFO is read. Therefore, the SR should be read prior to reading the corresponding data character. 12 Objective specification SC28L202 ...
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... Wake Up Mode (Also the “9–bit”, “multi–drop”, “party; line” or Special mode) The SC28L202 provides four modes of this common asynchronous ”party line” protocol where the parity bit is used to indicate that a byte is address data or information data. Three automatic modes and the default Host operated mode are provided ...
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... CIR unless the source has been enabled by the appropriate bit in an IMR. An interrupt source is active presenting its bid to the interrupt arbiter for evaluation. Most sources have simple activation requirements. The watch–dog timer, break received, Xon/Xoff or 14 Objective specification SC28L202 ...
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... Bit 2 Bit Objective specification SC28L202 Bit 0 Channel No. Channel No. Channel No. Channel No. Channel No. Channel No. Port Channel No. Counter Channel No. 0 ...
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... CPU occurs. The CIR loads with x’00 if Update CIR is asserted when the arbitration circuit has NOT detected an arbitration value that exceeds the threshold value of the ICR. The global registers and CIR may be used as “vectors” to the service type required. 16 Objective specification SC28L202 ...
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... Auto–transmitter mode When a channel receiver loads a Xoff character into the RxFIFO, the channel transmitter will finish transmission of the current character and then stop transmitting. A transmitter so idled can be restarted by the receipt of a Xon character by the receiver hardware or 17 Objective specification SC28L202 ...
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... Normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data. While this method is fully supported in the SC28L202 it also supports recognition of the character itself. Upon recognition of its address the receiver will be enabled and data loaded onto the RxFIFO. ...
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... Each channel has 3 mode registers (MR0 which control the basic configuration of the channel. Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Table 2 for register bit descriptions. 19 Objective specification SC28L202 ...
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... Reserved 2000 Feb 10 facilitate this feature the complete register function and control of the SC26C92 is replicated in the SC28L202. That is code written for the SCN2681, SCN68681, SCC2692, SCC68692 and SC26C92 will operate with this device. With the execution of code written for previous DUARTs and immediately after a hardware reset or a “ ...
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... Bit 2 Counter/Timer Channel B Channel A 0 Clock Select Rx/Tx Rx/Tx Clock Clock Selection Selection 0 = Default 0 = Default 0 = Default 1 = Enhanced 1 = Enhanced 1 = Enhanced 21 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 Memory Test Scan Test Iddq Test Bit 2 Bit 1 Bit 0 Address Xon Xoff Recognition Yes 1 = Yes ...
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... See Table 13 for the group organization. 000 Normal mode 001 Extended mode I 100 Extended mode II Other combinations of MR2[2:0] should not be used NOTE: MR0[3:0] are not used in channel B and should be set Objective specification SC28L202 (TEST 3) BIT 1 BIT 0 Reserved BAUD RATE Set to 0 EXTENDED 1 ...
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... MR1[1:0] – Bits per Character Select This field selects the number of data bits per character to be transmitted and received. This number does not include the start, parity, or stop bits. 23 Objective specification SC28L202 Bit 2 Bit 1:0 Parity Type Bits per Character 0 = Even ...
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... If an external 1X clock is used for the transmitter, MR2[ selects one stop bit and MR2[ selects two stop bits to be transmitted. 24 Objective specification SC28L202 BIT 1 BIT 0 ...
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... Interrupt generation is controlled by the channel IMR. The interrupt may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. See further description in the section on the Wake Up mode. 25 Objective specification SC28L202 Bit 1:0 Address Recognition control 00 = Default 01 = Auto wake ...
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... Tx A Clock Select Code 11 0000 to 11 1101 11 1110 11 1111 TxC Channel B I/O5 A 16x I/ Objective specification SC28L202 Clock selection, Sclk = 14.7456 MHz BRG – 75 BRG – 150 BRG – 450 BRG – 1800 BRG – 2000 BRG – 14.4K BRG – 19.2K BRG – 28.8K BRG – ...
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... Reserved 10101 Reserved. 10110 Transmitter resume command (This command is not active in “Auto–Transmit mode”). A command to cancel a previous Host Xoff command. Upon receipt, the channel’s transmitter will transfer a character, if any, from the TxFIFO and begin transmission. 27 Objective specification SC28L202 ...
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... Host Xoff Command (CRTXoff) 1 1000 Cancel Transmit X Char Command (CRTX) 1 1001 Reserved 1 1010 Reserved 1 1011 Reset Address Recognition Status 1 1100 Reserved 1 1101 Block Error Status on RxFIFO Read 1 1110 Reserved 1 1111 Reset Device as a Hardware reset. Reserved in channel B* 28 Objective specification SC28L202 ...
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... RxFIFO to be read by the CPU set when the character is transferred from the receive shift register to the RxFIFO and reset when the CPU reads the RxFIFO, and no more characters are in the RxFIFO. 29 Objective specification SC28L202 Bit 2 Bit 1 Bit 0 TxRDY RxFULL ...
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... It is the fact that this bit is zero (0) when the TxFIFO is full that stops a full TxFIFO from entering the interrupt arbitration. Also note that the meaning if this bit is not quite the same as the similar bit in the status register (SR). 30 Objective specification SC28L202 Bit 0 TxINT Transmitter entered the arbitration process. ...
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... See MR1[5] and ”RxFIFO Status” descriptions for ”block error” status reporting. Briefly, ”Block Error” gives the accumulated error of all bytes received by the RxFIFO since the last “Reset Error” command was issued. (CR = 0x04) 31 Objective specification SC28L202 Bit 2 Bit 1 Bit 0 Break Change RxRDY ...
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... An 8–bit character register that contains the compare value for a Xoff character. ARCR – Address Recognition Character Register A and B Bits 7:0 8 Bits of the Multi–Drop Address Character Recognition (Resets to 0x00 bit character register that contains the compare value for the wake–up address character 2000 Feb 10 32 Objective specification SC28L202 ...
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... Xon action causing any Xon/Xoff or wakeup mode activities to occur. The recognition event is reported in the ISR register. * This bit control is duplicated at MR0[7]. 33 Objective specification SC28L202 Bits 1:0 TxD character status 00 = normal TxD data 01 = Idle wait for FIFO data 10 = Xoff in pending 11 = Xon in pending ...
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... In other words the receivers and transmitters will always be in the 16x ode of operation when the internal BRG timer is selected for their clock. 34 Objective specification SC28L202 ...
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... I/O pin will have no effect on the operation of the transmitter. MR1 (7) is the bit that allows the receiver to control I/O0 B. When the receiver controls I/O0 B (or I/O1 B), the meaning of that pin will be the RTSN function. 35 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 ...
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... If CIR[ then a receiver interrupt is pending and the count is CIR[5:1], channel is CIR[0] Else If CIR[ then a transmitter interrupt is pending and the count is CIR[5:1], channel is CIR[0] Else the interrupt is another type, specified in CIR[5:1] NOTE: The GIBCR, Global Interrupting Byte Count Register, may be read to determine an exact character count. 36 Objective specification SC28L202 ...
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... Bit 4:3 Bit 2:0 Reserved Other types read 0x00 000 = not ”other” type 001 = Change of State 010 = Address Recognition Event 011 = Xon/Xoff status 37 Objective specification SC28L202 100 = Rx Watchdog 101 = Break Change 110 = Counter Timer 111 = Rx Loop Back Error ...
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... Reads the actual logic level at the pin change 1 = high level low level Bit 4 Bit 3 Bit 2 I/O4 n enable I/O3 n enable I/O2 n enable 0 = disable 0 = disable 0 = disable 1 = enable 1 = enable 1 = enable 38 Objective specification SC28L202 Bit 2 Bit 1 Bit 0 I/O2 n state I/O1 n state I/O0 n state Bit 1 Bit 0 I/O5 n state I/O4 n state Bit 1 Bit 0 I/O1 n enable I/O0 n enable 0 = disable ...
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... BIT 4 BIT 3 OPR 5 OPR 4 OPR 3 1=set bit 1=set bit 1=set bit 0=no 0=no change 0=no change change 39 Objective specification SC28L202 Bits 1:0 I/O0 A control 00 = GPI / CTSN OPR[ – Reserved Bits 1:0 I/O4 A control 00 = GPI / RxC A / PBRG 0 Clk Input 01 = OPR[ RxC A (16X) Output 11 = Reserved Bits 1:0 I/O0 B control ...
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... Command Register B ( Holding Register B (TxFIFO B) IVR or general purpose register Output Port Confide. Register (OPCR) I/O(7:2) B Set Output Port Bits Command (SOPR) I/O(7:0) B Reset output Port Bits Command (ROPR) I/O(7: Objective specification SC28L202 BIT 2 BIT 1 BIT 0 OPR 2 OPR 1 OPR 0 1=reset bit 1=reset bit ...
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... Reset Output Port ERROR (%) NORMAL RATE (BAUD) 0 2400 0 4800 –0.069 7200 0.059 9600 0 19.2K 0 38.4K 0 14.4K 0 28.8K –0.260 31.25 0 57.6k 0 115.2K 0.175 230.4K 41 Objective specification SC28L202 IPCR R ACR W ISR R IMR W CTPU R CTPL R CTPU W CTPL W IPR R OPCR W Bits W Bits W ACTUAL 16X ERROR (%) CLOCK (KHz) 38 ...
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... See Table 13 for the group organization. 000 Normal mode 001 Extended mode I 100 Extended mode II Other combinations of MR2[2:0] should not be used NOTE: MR0[3:0] are not used in channel B and should be set Objective specification SC28L202 BIT 1 BIT 0 TEST 2 BAUD RATE Set to 0 EXTENDED Normal ...
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... NOTE: Add 0.5 to binary codes 0 – 7 for 5 bit character lengths 0.563 4 = 0.813 8 = 1.563 C = 1.813 1 = Yes 1 = 0.625 5 = 0.875 9 = 1.625 D = 1.875 2 = 0.688 6 = 0.938 A = 1.688 E = 1.938 3 = 0.750 7 = 1.000 B = 1.750 F = 2.000 See description in the previous MR2 description 43 Objective specification SC28L202 BIT 2 Bits (1:0) PARITY BITS PER TYPE CHARACTER Even ...
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... SR B – Channel B Status Register The bit definitions for this register are identical to the bit definitions for SR A, except that all status applies to the Channel B receiver and transmitter and the corresponding inputs and outputs. 44 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 TxRDY FFULL ...
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... BIT 5 BIT 4 BIT 3 the upper and lower four bits in the same bus cycle. If both enable and disable bits are set the lower four bits a disable will result. 45 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 MR0[ (Extended Mode II) ACR[ ACR[ 4,800 7,200 ...
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... However it clouds the ability to know precisely which byte(s) are in error. 1110 Power Down Mode On 1111 Disable Power Down Mode 46 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 Enable Tx Disable Rx Enable Rx ...
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... Counter 001 Counter 010 Counter 011 Counter 100 Timer 101 Timer 110 Timer 111 Timer NOTE: The timer mode generates a square wave. 47 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 I/O 2A I low 0 = low 0 = low 1 = High 1 = High 1 = High BIT 1 BIT 0 Delta Delta I/O1 A interrupt ...
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... Ready 0=not 0=not 0=not enabled enabled enabled 1=enabled 1=enabled 1=enabled BIT 4 BIT 3 BIT 4 BIT 3 BIT 4 BIT 3 48 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 Delta RxRDY/ TxRDY A Break A FFULL A 0=not enabled 0=not enabled 0=not enabled 1=enabled 1=enabled 1=enabled BIT 2 BIT 1 BIT 0 Delta ...
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... The 1X clock for the Channel A transmitter that shifts the transmitted data. If data is not being transmitted, a free running 1X clock is output. 11 The 1X clock for the Channel A receiver that samples the received data. If data is not being received, a free running 1X clock is output. 49 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 BIT 2 ...
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... BIT 5 BIT 4 BIT 3 I/O5 B I/O4 B I/O3 B 0=Pin High 0=Pin High 0=Pin High 1=Pin Low 1=Pin Low 1=Pin Low 50 Objective specification SC28L202 BIT 2 BIT 1 BIT 0 I/O2 B I/O1 B I/O0 B 1=set bit 1=set bit 1=set bit 0=no change 0=no change 0=no change BIT 2 BIT 1 BIT 0 I/O2 B I/O1 B ...
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... Philips Semiconductors Dual UART REGISTER MAPS The registers of the SC28L202 are LOOSELY partitioned into two groups: those used in controlling data channels and those used in handling the actual data flow and status. Below is shown the general configuration of all the register addressed. The ”Register Map Summary” ...
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... Input Port Change Interrupt Enable (IPCE A) Programmable BRG Clock Source (PBRGCS) Programmable BRG Preset Lower (PBRGPL 1) Programmable BRG Preset Upper (PBRGPU 1) Receiver Clock Select Register (RxCSR B) Transmitter Clock Select Register (TxCSR B) Input Port Change Interrupt Enable (IPCE B) 52 Objective specification SC28L202 ...
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... Bidding Control Register – Break Change (BCRBRK B) Bidding Control Register – Change of State (BCRCOS B) Bidding Control Register – Counter/Timer (BCRCT B) Bidding Control Register – Xon (BCRx B) Bidding Control Register – Address (BCRA B) Bidding Control Register – Loop Back Error (BCRLBE B) 53 Objective specification SC28L202 ...
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... Feb 10 WRITE Interrupt Control Register (ICR) Update Current Interrupt Register (UCIR) Interrupt Vector Register (IVR) Global Chip Configuration Register (GCCR) Test & Revision Register (TRR) Global TxFIFO Register (GTxFIFO) Scan Test Control Register (STCR) 54 Objective specification SC28L202 ...
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... This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. 2000 Feb 10 2 –0 Objective specification SC28L202 RATING UNIT 4 Note C –65 to +150 C –0.5 to +7.0 V – ...
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... CMOS input levels CMOS input levels –0.2V and Objective specification SC28L202 LIMITS UNIT Min Typ Max 1.2 0.8 V 2.4 1.5 V 0.8*Vcc 2.4 V 0.2 0.4 V Vcc – 0.5 v 0.5 0.05 0.5 A –130 130 A –0.5 ...
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... DACKN High from CSN or IACKN high DAH t DACKN High impedance from CSN or IACKN high DAT t CSN or IACKN setup time to X1 high for minimum DACKN cycle CSC 2000 Feb 10 7 5,7 57 Objective specification SC28L202 4 LIMITS Min Typ Max UNIT 100 ...
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... If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must be negated for t RWD time to guarantee that any status register changes are valid. 8. Minimum frequencies are not tested but are guaranteed by design. 9. Clocks for 1X mode should be symmetrical. 2000 Feb pF Objective specification SC28L202 = 2.7K ohm ...
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... CMOS input levels CMOS input levels –0.2V and Objective specification SC28L202 LIMITS UNIT Min Typ Max 0.65 0.2*Vcc V 0.8*Vcc 1.7 V 0.2 0.4 V Vcc–0.5 Vcc–0.2 v –0.5 0.05 +0.5 A – – ...
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... Objective specification SC28L202 Max UNIT MHz ns 8 MHz ...
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... Figure 3. Reset Timing (68XXX mode) 2000 Feb 10 t RES SD00133 Figure 1. Reset Timing (80XXX mode RWD NOT VALID FLOAT VALID t RWD VALID Figure 2. Bus Timing (80XXX mode) SD00109 61 Objective specification SC28L202 = 50 pF 2.7K ohm SD00087 ...
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... Figure 5. Bus Timing (Write Cycle) (68XXX mode) 2000 Feb 10 t CSC RWD NOT DATA VALID VALID t DCR t DAT t CSC DCW t DAT 62 Objective specification SC28L202 DAH SD00687 RWD DAH SD00688 ...
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... IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 2000 Feb 10 t CSC CSD t DAL t t DCR DAH Figure 6. Interrupt Cycle Timing (68XXX mode OLD DATA Figure 7. Port Timing 63 Objective specification SC28L202 DAT SD00149 NEW DATA SD00135 ...
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... Figure 8. Interrupt Timing (80xxx mode) NOTE: RESISTOR REQUIRED FOR TTL INPUT. CLK t CLK t CTC t Rx *NOTE: X2 MUST BE LEFT OPEN SC28L92 X1 2pF 50k to 100k 4pF X2 14.7456MHz Figure 9. Clock Timing 64 Objective specification SC28L202 V +0. +0. SD00136 V CC 470 X1 X2* TO UART CIRCUIT SD00689 ...
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... BIT TIME ( CLOCKS) t TXD t TCS Figure 10. Transmitter External Clocks t t RXS RXH Figure 11. Receiver External Clock D2 D3 BREAK D9 START D10 STOP BREAK BREAK Figure 12. Transmitter Timing 65 Objective specification SC28L202 SD00138 SD00139 D4 D6 D11 WILL D12 NOT BE WRITTEN TO THE TxFIFO OPR( SD00155 ...
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... BIT 9 BIT MR1( ADD#2 BIT 9 BIT ADD#1 STATUS DATA D0 Figure 14. Wake-Up Mode 66 Objective specification SC28L202 D11 D12 D13 D12, D13 WILL BE LOST DUE TO RECEIVER DISABLE. STATUS DATA STATUS DATA D2 D3 D10 RESET BY COMMAND SD00156 BIT 9 ADD#2 1 BIT 9 BIT 9 ...
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... Philips Semiconductors Dual UART I = 2.4mA INTRN DACKN 125pF I = 2.4mA V return 400 A V return D0–D7 TxDA/B OP0–OP7 125pF Figure 15. Test Conditions on Outputs 2000 Feb 10 +5V for a 0 level CC for a 1 level SS SD00690 67 Objective specification SC28L202 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 2.0 mm 2000 Feb 10 68 Objective specification SC28L202 SOT379-1 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm 2000 Feb 10 69 Objective specification SC28L202 SOT364-1 ...
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... Philips Semiconductors Dual universal asynchronous receiver/transmitter (DUART) 2000 Feb 10 NOTES 70 Objective specification SC28L202 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 2000 Feb 10 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 71 Objective specification SC28L202 All rights reserved. Printed in U.S.A. Date of release: 02-00 9397 750 06826 ...