SC28L91 Philips Semiconductors, SC28L91 Datasheet
SC28L91
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SC28L91 Summary of contents
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... SC28L91 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART) Product specification Supersedes data of 2000 Apr 03 hilips Semiconductors INTEGRATED CIRCUITS 2000 Sep 22 ...
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... Philips Semiconductors 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART) DESCRIPTION The SC28L91 is a new member of the IMPACT family of Serial Communications Controllers single channel UART operating at 3.3 and 5.0 volts Vcc byte FIFOs and is quite compatible with software of the SC28L92 and previous UARTs offered by Philips ...
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... Philips Semiconductors 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART) ORDERING INORMATION Description 44-Pin Plastic Leaded Chip Carrier (PLCC) 44-Pin Plastic Quad Flat Pack (PQFP) 2000 Sep 22 Industrial V = +3.3 10%, +5V 10 –40 to +85 C Drawing Number amb SC28L91A1A SOT187-2 SC28L91A1B SOT307-2 3 Product specification SC28L91 ...
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... IP0 WRN RDN 41 IP3 I/M 43 IP1 13 No Connection OP1 15 OP3 SD00698 4 Product specification SC28L91 PLCC Pin Function Pin Function 16 OP5 31 OP2 17 OP7 32 OP0 TxDA RxDA 21 ...
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... IP0 R/ DACKN 41 IP3 I/M 43 IP1 13 No Connection OP1 15 OP3 SD00700 5 Product specification SC28L91 PLCC Pin Function Pin Function 16 OP5 31 OP2 17 OP7 32 OP0 TxDA RxDA 21 D7 ...
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... CTL CTU 2000 Sep 22 DATA CHANNEL 16 BYTE TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE WATCH DOG TIMER DETECTORS (4) SELECT LOGIC Figure 1. Block Diagram (80XXX mode) 6 Product specification SC28L91 TxDA FIFO TRANSMIT FIFO RxDA RECEIVE SHIFT REGISTER MRA0 CRA SRA INPUT PORT CHANGE OF ...
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... CTL CTU 2000 Sep 22 DATA CHANNEL 16 BYTE TRANSMIT SHIFT REGISTER 16 BYTE RECEIVE WATCH DOG TIMER DETECTORS (4) SELECT LOGIC Figure 2. Block Diagram (68XXX mode) 7 Product specification SC28L91 TxDA FIFO TRANSMIT FIFO RxDA RECEIVE SHIFT REGISTER MRA0 CRA SRA INPUT PORT CHANGE OF ...
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... Input 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP5 I Input 5: General-purpose input IP6 I Input 6: General-purpose input V Pwr Power Supply: +3.3 or +5V supply input 10% CC GND Pwr Ground 2000 Sep 22 8 Product specification SC28L91 ...
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... Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP5 I Input 5: General purpose input. V Pwr Power Supply: +3.3 or +5V supply input 10% CC GND Pwr Ground 2000 Sep 22 9 Product specification SC28L91 ...
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... CMOS input levels CMOS input levels . All time measurements are referenced at input voltages of 0.8V and CC when the input pins are -0.2 V and Product specification SC28L91 Rating Unit Note 4 C –65 to +150 C –0.5 to +7.0 V –0 +0 2 ...
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... CMOS input levels CMOS input levels . All time measurements are referenced at input voltages of 0.8 V and CC when the input pins are –0.2 V and Product specification SC28L91 Min Typ Max Unit 0.65 0.2 0.8*V 1 0.2 0 –0.5 V –0.2 ...
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... Transmitter Timing, external clock (See Figure 12) t TxD output delay from TxC low (TxC input pin) *TXD t Output delay from TxC output pin low to TxD data output *TCS 2000 Sep Product specification SC28L91 Min Typ Max Unit 100 ...
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... It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle ...
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... Transmitter Timing, external clock (See Figure 12) t TxD output delay from TxC low (TxC input pin) *TXD t Output delay from TxC output pin low to TxD data output *TCS 2000 Sep Product specification SC28L91 Min Typ Max Unit 100 ...
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... It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the bus cycle ...
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... Philips Semiconductors 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART) Block Diagram The SC28L91 UART consists of the following seven major sections: data bus buffer, operation control, interrupt control, timing, Rx and Tx FIFO Buffers, input port and output port control. Refer to the Block Diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses ...
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... ISR will return a x’00 character. This action may present the appearance of a spurious interrupt. Communications The communications channel of the SC28L91 comprises a full-duplex asynchronous receiver/transmitter (UART). The operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter/timer, or from an external input ...
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... DMA control. OPERATION Transmitter The SC28L91 is conditioned to transmit data when the transmitter is enabled through the command register. The SC28L91 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN ...
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... When operating in the special time out mode possible to generate what appears “false interrupt”, i.e. an interrupt without a cause. This may result when a time-out interrupt occurs and then, BEFORE the interrupt is serviced, another character is received, i.e., the data stream has started again. (The interrupt 19 Product specification SC28L91 ...
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... In this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. If disabled, it sets the RxRDY status bit and loads the character into the RxFIFO if the received A/D bit is a one (address tag), but discards the received Table 1. SC28L91 register addressing Address Bits READ (RDN = 0) A[3:0] ...
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... Set to 0 Counter Ready State State State Configure Configure Configure OP3 OP5 OP4 Set OP 5 Set OP 4 Set OP 3 Reset OP 5 Reset OP 4 Reset Product specification SC28L91 IMR W CTU R CTL R CTPU W CTPL W IPR R OPCR W Bits W Bits W IVR/GP ...
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... These bits are used to select one of the six–baud rate groups. See Table 5 for the group organization. 000 Normal mode 001 Extended mode I 100 Extended mode II Other combinations of MR2[2:0] should not be used. 22 Product specification SC28L91 BIT 1 BIT 0 TEST 2 BAUD RATE EXTENDED 1 Set Normal ...
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... MR1[1:0]— Bits Per Character Select This field selects the number of data bits per character to be transmitted and received. The character length does not include the start, parity, and stop bits. 23 Product specification SC28L91 BIT 2 BIT 1 BIT 0 PARITY TYPE BITS PER ...
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... Program auto–reset mode: MR2[ Enable transmitter. 3. Asset RTSN: OPR[ Send message. 5. Disable transmitter after the last character is loaded into the TxFIFO. 24 Product specification SC28L91 BIT 1 BIT 1.563 C = 1.813 9 = 1.625 D = 1.875 A = 1.688 E = 1.938 ...
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... If an external 1X clock is used for the transmitter, then MR2[ selects one stop bit and MR2[ selects two stop bits to be transmitted. 25 Product specification SC28L91 ...
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... Timer IP4–16X IP4–16X IP4–1X IP4–1X ACTUAL 16X CLOCK (KHz) 0.8 1.2 1.759 2.153 2.4 3.2 4.8 9.6 16.756 19.2 28.8 32.056 38.4 76.8 115.2 153.6 307.2 614.4 26 Product specification SC28L91 MR0[ (Extended Mode II) ACR[ ACR[ 4,800 7,200 880 880 1,076 1,076 19.2K 14.4K 28.8K 28.8K 57.6K 57.6K 115.2K 115.2K 1,050 2,000 57.6K 57.6K 4,800 4,800 57.6K 14.4K ...
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... See Operation section. CR[0]—Enable Receiver Enables operation of the receiver. If not in the special wakeup mode, this also forces the receiver into the search for start–bit state. 27 Product specification SC28L91 BIT 2 BIT 1 BIT 0 Enable Tx Disable Rx Enable Rx ...
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... FIFO to be read by the CPU set when the character is transferred from the receive shift register to the FIFO and reset when the CPU reads the receive FIFO, only if (after this read) there are no more characters in the FIFO – the Rx FIFO becomes empty. 28 Product specification SC28L91 BIT 2 BIT 1 BIT 0 TxRDY FFULL ...
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... set bit 1 = set bit change change BIT 4 BIT reset bit 1 = reset bit change change 29 Product specification SC28L91 BIT 2 BIT 1 BIT 0 OP2 OP1 OP0 00 = OPR[ TxC(16X TxC(1X RxC(1X) BIT 2 BIT 1 BIT ...
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... High IPCR [3:0]—IP3, IP2, IP1, IP0 Change-of-State These bits provide the current state of the respective inputs. The information is unlatched and reflects the state of the input pins at the time the IPCR is read. 30 Product specification SC28L91 BIT 2 BIT 1 BIT ...
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... This register stores the Interrupt Vector initialized to 0x0F on hardware reset and is usually changed from this value during initialization of the SC28L91 for the 68K Mode. The contents of this register will be placed on the data bus when IACKN is asserted low or a read of address 0xC is performed. ...
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... MR2[4] is set to zero, the IP pin will have no effect on the operation of the transmitter. MR1[7] is the bit that allows the receiver to control OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be. 32 Product specification SC28L91 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 ) ...
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... Bus action in the 80XXX mode terminates on the rise of CEN, WRN, or RDN which ever one occurs first. 2000 Sep 22 RESETN Figure 4. Reset Timing RWD NOT VALID FLOAT VALID t RWD VALID Figure 5. Bus Timing (80XXX mode) 33 Product specification SC28L91 t RES 68XXX Mode SD00696 SD00087 ...
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... Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first. 2000 Sep 22 t CSC RWD NOT DATA VALID VALID t DCR t DAT t CSC DCW t DAT 34 Product specification SC28L91 DAH SD00687 RWD DAH SD00688 ...
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... IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 2000 Sep 22 t CSC CSD t DAL t t DCR DAH Figure 8. Interrupt Cycle Timing (68XXX mode OLD DATA Figure 9. Port Timing 35 Product specification SC28L91 DAT SD00149 NEW DATA SD00135 ...
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... Figure 10. Interrupt Timing (80xxx mode) NOTE: RESISTOR REQUIRED FOR TTL INPUT. CLK t CLK t CTC t Rx *NOTE: X2 MUST BE LEFT OPEN SC28L91 X1 2pF 50k to 100k 4pF X2 3.6864MHz Figure 11. Clock Timing 36 Product specification SC28L91 V +0. +0. SD00136 V CC 470 X1 X2* TO UART CIRCUIT SD00704 ...
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... BIT TIME ( CLOCKS) t TXD t TCS Figure 12. Transmitter External Clocks t t RXS RXH Figure 13. Receiver External Clock D2 D3 BREAK D9 START D10 STOP BREAK BREAK Figure 14. Transmitter Timing 37 Product specification SC28L91 SD00138 SD00139 D4 D6 D11 WILL D12 NOT BE WRITTEN TO THE TxFIFO OPR( SD00155 ...
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... BIT 9 BIT MR1( ADD#2 BIT 9 BIT ADD#1 STATUS DATA D0 Figure 16. Wake-Up Mode 38 Product specification SC28L91 D11 D12 D13 D12, D13 WILL BE LOST DUE TO RECEIVER DISABLE. STATUS DATA STATUS DATA D2 D3 D10 RESET BY COMMAND SD00156 BIT 9 ADD#2 1 BIT 9 BIT 9 ...
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... Philips Semiconductors 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART 2.4mA INTRN DACKN 125pF I = 2.4mA V return 400 A V return D0–D7 TxDA/B OP0–OP7 125pF Figure 17. Test Conditions on Outputs 2000 Sep 22 +5V for a 0 level CC for a 1 level SS SD00690 39 Product specification SC28L91 ...
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... Philips Semiconductors 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART) PLCC44: plastic leaded chip carrier; 44 leads 2000 Sep 22 40 Product specification SC28L91 SOT187-2 ...
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... Philips Semiconductors 3.3V–5.0V Universal Asynchronous Receiver/Transmitter (UART) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 2000 Sep 22 41 Product specification SC28L91 SOT307-2 ...
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... Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 hilips Semiconductors 2000 Sep 22 [1] Copyright Philips Electronics North America Corporation 2000 Document order number: 42 Product specification SC28L91 All rights reserved. Printed in U.S.A. Date of release: 09-00 9397 750 07549 ...