sl28pcie14 Silicon Laboratories, sl28pcie14 Datasheet
sl28pcie14
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sl28pcie14 Summary of contents
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... Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Industrial Temperature -40 • 3.3V Power supply • 32-pin QFN package Pin Configuration SRC [3:0] OE_SRC [3: Internal 100K-ohm pull-upresistor ** Internal 100K-ohm pull-down resistor 1+(512) 416-8500 1+(512) 416-9669 SL28PCIe14 ® Technology Page www.silabs.com ...
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... LOW) 3.3V Power Supply O 25.00MHz Crystal output, Float XOUT if using only CLKIN (Clock input) I 25.00MHz Crystal input or 3.3V, 25MHz Clock Input I True differential serial reference clock input I Complement differential serial reference clock Ground SL28PCIe14 Description Frequency Spread Note 100M OFF Default 100M -0.5% 100M -/+0 ...
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... Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description Block Read Protocol Bit 1 Start SL28PCIe14 Description Page ...
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... Acknowledge from slave 18:11 Command Code–8 bits 19 Acknowledge from slave 20 Repeated start 27:21 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave–8 bits 38 NOT Acknowledge 39 Stop Name RESERVED RESERVED SL28PCIe14 Block Read Protocol Description Byte Read Protocol Description Description Page ...
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... Output enable for SRC3 0 = Output Disabled Output Enabled RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Name SL28PCIe14 Description Description Description Description Page ...
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... PD#. After a valid rising edge on CKPWRGD/PD# pin, a time of not more than 1.8ms is allowed for the clock device’s internal PLL’s to power up and lock. After this time, all outputs are enabled in a glitch-free manner within a few clock cycles of each clock SL28PCIe14 Description Page ...
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... V DD Except internal pull-up resistors, 0 < – Differential clocks with 5” traces and 2pF load, frequency at 100MHz. Differential clocks with 5” traces and 2pF load, frequency at 100MHz. SL28PCIe14 Min. Max. Unit – 4.6 V –0.5 4 –65 150 °C – ...
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... Includes PLL MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz Includes PLL MHz, CDR = 10MHz) Measured at 0V differential In buffer mode. Measured at 0V differential Measured at 0V differential Measured differentially from ±150 mV SL28PCIe14 Min. Max. Unit – 250 ppm ...
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... Test and Measurement Set-up For Differential Clock Signals This diagram shows the test load configuration for the differential clock signals Figure 1. 0.7V Differential Load Configuration Figure 2. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0014 (Rev. AA) SL28PCIe14 Page ...
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... Figure 3. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) DOC#: SP-AP-0014 (Rev. AA) SL28PCIe14 Page ...
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... SL28PCIe14ALI 32-pin QFN SL28PCIe14ALIT 32-pin QFN – Tape and Reel Package Diagrams DOC#: SP-AP-0014 (Rev. AA) Package Type 32-Lead QFN 5x 5mm SL28PCIe14 Product Flow Commercial, 0 to 85C Commercial, 0 to 85C Industrial, -40 to 85C Industrial, -40 to 85C Page ...
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... Document History Page Document Title: SL28PCIe14 PC PCI-Express Gen 2 & Gen 3 Clock Generator & Fan-out Buffer with EProClock Technology DOC#: SP-AP-0014 (Rev. AA) Orig. of REV. ECR# Issue Date Change AA 1695 02/09/11 JMA DOC#: SP-AP-0014 (Rev. AA) Description of Change Initial Release SL28PCIe14 ® Page ...
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... Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. DOC#: SP-AP-0014 (Rev. AA) SL28PCIe14 Page ...