STPCI2 STMicroelectronics, STPCI2 Datasheet
STPCI2
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X86 Core PC Compatible System-on-Chip for Terminals POWERFUL x86 PROCESSOR 64-BIT SDRAM UMA CONTROLLER GRAPHICS CONTROLLER - VGA & SVGA CRT CONTROLLER - 135MHz RAMDAC - ENHANCED 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR ...
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STPC ATLAS DESCRIPTION The STPC Atlas integrates a standard 5th generation x86 core along with a powerful UMA graphics/video chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with standard I/O interfaces to provide ...
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TFT Interface Programmable panel size up to 1024 by 1024 pixels. Support for VGA and SVGA active matrix TFT flat panels with 9, 12, 18-bit interface (1 pixel per clock). Support for XGA and SXGA active matrix TFT flat panels ...
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STPC ATLAS PCMCIA interface Support one PCMCIA 68-pin standard PC Card Socket. Power Management support. Support PCMCIA/ATA specifications. Support I/O PC Card with pulse-mode interrupts. USB Interface USB 1.1 compatible. Open HCI 1.0 compliant. User configurable RootHub. Support for ...
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GENERAL DESCRIPTION At the heart of the STPC Atlas is an advanced processor block that includes a powerful x86 processor core along with a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed PCI bus ...
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GENERAL DESCRIPTION The STPC Atlas implements a multi-function parallel port. The standard PC/AT compatible logical address assignments for LPT1, LPT2 and LPT3 are supported. It can be configured for any of the following three modes and supports the IEEE Standard ...
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Figure 1-1. Functional description. Host x86 I/F Core PCI m/s LB CTRL Video Pipeline SVGA CRTC GE I/F VIP SDRAM CTRL Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION USB PCI Bus PMU I/Os ISA PCI IPC m/s m/s ISA ...
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GENERAL DESCRIPTION 1.7. CLOCK TREE The STPC Atlas integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2. VCLK VIP CRTC,Video,TFT 48MHz DEVCLK PLL 1/6 UARTs ...
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Figure 1-3. Typical ISA-based Application. RTC 5V tolerant Flash Boot ISA ROMCS# IRQ DMA.ACK DMA.REQ PCI EIDE USB STPC Atlas SDRAM Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION SVGA TFT 2 Serial Ports Keyboard Parallel Port Mouse VIP 16 ...
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GENERAL DESCRIPTION Figure 1-4. Typical PCMCIA-based Application. 5V tolerant PCMCIA ROMCS# PCI 10/111 EIDE USB Flash Boot STPC Atlas SDRAM Issue 1.0 - July 24, 2002 SVGA TFT 2 Serial Ports Keyboard Parallel Port Mouse VIP 16 GPIOs ...
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Figure 1-5. Typical Local-Bus-based Application. RTC Flash Boot Local Bus IRQ PCI EIDE USB STPC Atlas SDRAM Issue 1.0 - July 24, 2002 GENERAL DESCRIPTION SVGA TFT 2 Serial Ports Keyboard Parallel Port Mouse VIP 16 GPIOs 11/111 ...
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GENERAL DESCRIPTION 12/111 Issue 1.0 - July 24, 2002 ...
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PIN DESCRIPTION 2.1. INTRODUCTION The STPC Atlas integrates functionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Atlas. This offers improved performance ...
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PIN DESCRIPTION Signal Name Dir Buffer Type BASIC CLOCKS AND RESETS SYSRSTI# I SCHMITT_FT SYSRSTO# O BD8STRP_FT XTALI I OSCI13B XTALO O PCI_CLKI I TLCHT_FT PCI_CLKO O BT8TRP_TC ISA_CLK, O BT8TRP_TC ISA_CLK2X OSC14M O BD8STRP_FT HCLK I/O BD4STRP_FT DEV_CLK O ...
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Signal Name Dir Buffer Type ISA BUS INTERFACE LA[23:17] O BD8STRUP_FT SA[19:0] O BD8STRUP_FT SD[15:0] I/O BD8STRP_FT IOCHRDY I BD8STRUP_FT ALE O BD4STRP_FT BHE# O BD8STRUP_FT MEMR#, MEMW# I/O BD8STRUP_FT SMEMR#, SMEMW# O BD8STRP_FT IOR#, IOW# I/O BD8STRUP_FT MASTER# I ...
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PIN DESCRIPTION Signal Name Dir Buffer Type LOCAL BUS INTERFACE PA[24:20,15,9:8,3:0] O BD4STRP_FT PA[19,11] O BD8STRP_FT PA[18:16,14:12,7:4] O BD8STRUP_FT PA[10] O BD4STRUP_FT PD[15:0] I/O BD8STRP_FT PRD# O BD4STRUP_FT PWR# O BD4STRUP_FT PRDY I BD8STRUP_FT IOCS#[7:4] O BD4STRUP_FT IOCS#[3] O BD4STRP_FT ...
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Signal Name Dir Buffer Type TFTB[5:2] O BD4STRP_TC TFTB[1:0] O BD4STRP_FT TFTLINE O BD8STRP_TC TFTFRAME O BD4STRP_TC TFTDE O BD4STRP_TC TFTENVDD, O BD4STRP_TC TFTENVCC TFTPWM O BD8STRP_TC TFTDCLK O BT8TRP_TC VIDEO INPUT PORT VCLK I/O BD8STRP_FT VIN[7:0] I BD4STRP_FT ODD_EVEN# ...
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PIN DESCRIPTION Signal Name Dir Buffer Type GPIO SIGNALS GPIO[15:0] I/O BD4STRP_FT JTAG TCLK I TLCHT_FT TRST I TLCHT_FT TDI I TLCHTD_FT TMS I TLCHT_FT TDO O BT8TRP_TC MISCELLANEOUS SCAN_ENABLE I TLCHTD_FT SPKRD O BD4STRP_FT 1 Note ; See Table ...
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SIGNAL DESCRIPTIONS 2.2.1. BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply’s power good signal. PWGD is asynchronous to all clocks, and acts as ...
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PIN DESCRIPTION CAS#[1:0] Column Address Strobe. There are two active-low column address strobe output signals. The CAS# signals drive the memory devices directly without any external buffering. MWE# Write Enable. Write enable specifies whether the memory access is a read ...
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STPC Atlas. The STPC Atlas monitors this signal as an input when performing an ISA cycle on behalf of the host CPU, DMA master or refresh. ISA masters which do not monitor IOCHRDY are not guaranteed to work with ...
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PIN DESCRIPTION IRQ_MUX[3:0] Multiplexed Interrupt Request. These are the ISA bus interrupt signals. They are to be encoded before connection to the STPC Atlas using ISACLK and ISACLKX2 as the input selection strobes. Note that IRQ8B, which by convention is ...
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VPP2 and VCC Card socket. Also see GPI# General Purpose Input. This signal is hardwired to 1. 2.2.6. LOCAL BUS PA[24:0] Address Bus Output. PD[15:0] Data Bus. This is the 16-bit data ...
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PIN DESCRIPTION RSET Resistor Current Set. This is the reference current input to the RAMDAC. Used to set the full- scale output of the RAMDAC. COMP Compensation. This is the RAMDAC compensation pin. Normally, an external capacitor (typically 10nF) is ...
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MCLK, Mouse Clock line. Mouse data is latched by the controller on each negative clock edge produced on this pin. The mouse can be disabled by pulling this pin low by software control. MDATA, Mouse Data Line. 11-bits of data ...
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PIN DESCRIPTION 2.3. SIGNAL DETAIL The muxing between ISA, LOCAL BUS and PCMCIA is performed by external strap options. Table 2-4. Multiplexed Signals (on the same pin) IDE Pin Name DIORDY IOCHRDY DA[2] LA[19] DA[1:0] LA[18:17] SCS3,SCS1 LA[23:22] PCS3,PCS1 LA[21:20] ...
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Signal Name BASIC CLOCKS AND RESETS XTALO ISA_CLK ISA_CLK2X OSC14M DEV_CLK HCLK PCI_CLKO DCLK MEMORY CONTROLLER MCLKO CS#[3:1] CS#[0] MA[10:0], BA[0] RAS#[1:0], CAS#[1:0] MWE#, DQM[7:0] MD[63:0] PCI INTERFACE AD[31:0] CBE[3:0], PAR FRAME#, TRDY#, IRDY# STOP#, DEVSEL# PERR#, SERR# PCI_GNT#[2:0] ISA ...
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PIN DESCRIPTION Signal Name FCS_0L#, FCS1#, FCS_1H#, FCS_1L# PWR#, IOCS#[7:0] IDE CONTROLLER DD[15:0] DA[2:0] PCS1, PCS3, SCS1, SCS3 PDACK#, SDACK# PDIOR#, PDIOW#, SDIOR#, SDIOW# VGA CONTROLLER RED, GREEN, BLUE VSYNC, HSYNC COL_SEL I2C INTERFACE SCL / DDC[1] SDA / DDC[0] ...
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Table 2-6. Pinout Pin# Pin Name D15 SYSRSETI# C15 SYSRSETO# AF21 XTALI AF22 XTALO AF23 PCI_CLKI AF24 PCI_CLKO E15 ISA_CLK A16 ISA_CLK2X AB18 OSC14M AB24 HCLK 1 AB25 DEV_CLK /FCS1# AC18 DCLK AF20 MCLKI AF19 MCLKO U5 MA[0] V1 MA[1] ...
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PIN DESCRIPTION Table 2-6. Pinout Pin# Pin Name E8 SERR# C8 LOCK# C14 PCI_REQ#[0] B14 PCI_REQ#[1] A14 PCI_REQ#[2] A13 PCI_GNT#[0] B13 PCI_GNT#[1] C13 PCI_GNT#[2] 1 C20 LA[17] 1 B21 LA[18] 1 B20 LA[19] 1 E19 LA[20] 1 E18 LA[21] 1 ...
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Table 2-6. Pinout Pin# Pin Name AE14 TFTB5 AB14 TFTLINE AC14 TFTFRAME AF15 TFTDE AE15 TFTENVDD AD15 TFTENVCC AC15 TFTPWM AD14 TFTDCLK D21 OC A20 USBDMNS[0] A18 USBDMNS[1] A21 USBDPLS[0] A19 USBDPLS[1] E20 POWERON AC22 CTS0# AC24 CTS1# AD21 DCD0# ...
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PIN DESCRIPTION Table 2-6. Pinout Pin# Pin Name F19 GND F21 GND H4 GND H21 GND H23 GND J6 GND L6 GND L11:16 GND L21 GND M6 GND M11:16 GND N11:16 GND N21 GND P6 GND P11:16 GND R11:16 GND ...
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STRAP OPTION This chapter defines the STPC Atlas Strap Options and their locations. Some strap options are left programmable for future versions of Signal Designation MD1 MD2 HCLK Speed MD3 PCI_CLKO Divisor MD[4] MD[5] MCLK Synchro (see MD[6] PCI_CLKO ...
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STRAP OPTION Signal Designation MD 45 CPUCLK/HCKL Deskew Programming Internal UART2 (see MD 51 Internal UART1 (see MD 52 Internal Kbd / Mouse (see MD 53 Internal Parallel Port (see 1 TC ...
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STRAP OPTION REGISTER DESCRIPTION 3.1.1. STRAP REGISTER 0 This register is read only. STRAP0 7 6 MD[7] MD[6] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bits 7-6 MD[7:6] Bits ...
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STRAP OPTION 3.1.2. STRAP REGISTER 1 This register is read only. STRAP1 7 6 MD[40] MD[14] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bits 7-6 MD[40] & MD[14] Bits 5-1 ...
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HCLK PLL STRAP REGISTER This register is read only. HCLK_STRAP0 7 6 RSV MD[26] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bits 7-6 Rsv Bits 5-3 MD[26:24] Bits 2-0 ...
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STRAP OPTION 3.1.4. STRAP REGISTER 2 This register is read only with the exception of bit 4 STRAP2 7 6 MD[53] MD[52] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bit ...
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CPUCLK/HCKL PROGRAMMING ; MD[45] MD[46] HCLK between 33MHz and 1 0 HCLK between 64MHz and 0 1 All other settings are reserved Table 3-1. Note that these straps are not accessible by software. DESKEW Description 64MHz 133MHz Issue 1.0 ...
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STRAP OPTION 3.2. TYPICAL STRAP OPTION IMPLEMENTATION Table Table 3-1.shows the detailed Strap options required to boot the STPC in ISA mode with a Signal MD1 MD2 MD3 MD[4] MCLK Synchro (see MD[5] MD[6] MD[7] MD[8] MD[9] MD10 MD11 MD14 ...
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Signal MD 45 CPUCLK/HCKL Deskew Programming Internal UART2 (see MD 51 Internal UART1 (see MD 52 Internal Kbd / Mouse (see MD 53 Internal Parallel Port (see DACK_ENC[2] 1 ...
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STRAP OPTION 42/111 Issue 1.0 - July 24, 2002 ...
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ELECTRICAL SPECIFICATIONS 4.1. INTRODUCTION The electrical specifications in this chapter are valid for the STPC Atlas. 4.2. ELECTRICAL CONNECTIONS 4.2.1. POWER/GROUND DECOUPLING Due to the high frequency of operation of the STPC Atlas necessary to install and ...
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ELECTRICAL SPECIFICATIONS 4.4. DC CHARACTERISTICS Symbol Parameter V 3.3V Operating Voltage DD V 2.5V Operating Voltage CORE P 3.3V Supply Power 2.5V Supply Power CORE V Input Low Voltage IL V Input High Voltage IH I Input ...
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Symbol WLC White Level Current Table 4-5. VGA RAMDAC Power Consumption DCLK (MHz) - 6.25 - 135 Table 4-6. 2.5V Power Consumptions (V HCLK CPUCLK MCLK (MHz) (MHz) (MHz) 66 133 (x2 133 (x2) 90 Note 1: PCI ...
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ELECTRICAL SPECIFICATIONS 4.5. AC CHARACTERISTICS This section lists the AC characteristics of the STPC interfaces including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 ...
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Figure 4-2. CLK Timing Measurement Points (MIN) V Ref V IL (MAX) CLK One Clock Cycle LEGEND Minimum Time Minimum Time Clock Fall Time ...
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ELECTRICAL SPECIFICATIONS 4.5.1. POWER ON SEQUENCE Figure 4-3 describes the power-on sequence of the STPC, also called cold reset. There is no dependency between the different power supplies and there is no constraint on their rising time. SYSRSTI ...
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RESET SEQUENCE Figure 4-4 describes the reset sequence of the STPC, also called warm reset. The constraints on the strap options and the bus activities are the same as for the cold reset. The SYSRSTI# pulse duration must be ...
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ELECTRICAL SPECIFICATIONS 4.5.3. SDRAM INTERFACE Figure 4-5, Table 4-10, Table 4-11 characteristics of the SDRAM interface. The MCLKx T delay MCLKI STPC.output STPC.input T hold Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range Name Parameter Tcycle MCLKI Cycle ...
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Table 4-11. SDRAM Bus AC Timings - Industrial Temperature Range Name Parameter Tcycle MCLKI Cycle Time Thigh MCLKI High Time Tlow MCLKI Low Time MCLKI Rising Time MCLKI Falling Time Tdelay MCLKx to MCLKI delay MCLKI to RAS# Valid MCLKI ...
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ELECTRICAL SPECIFICATIONS 4.5.4. PCI INTERFACE Figure 4-6 and Table 4-12 list the AC characteris- tics of the PCI interface. PCICLKx stands for any PCI device clock input. HCLK PCICLKx T clkx PCICLKI T hclk STPC.output STPC.input T hold Table 4-12. ...
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IPC INTERFACE Table 4-13 lists the AC characteristics of the IPC interface. ISACLK2X ISACLK IRQ_MUX[3:0] DREQ_MUX[1:0] Name Parameter T ISACLK2X to ISACLK delay dly ISACLK2X to DACK_ENC[2:0] valid ISACLK2X to TC valid T IRQ_MUX[3:0] Input setup to ISACLK2X setup ...
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ELECTRICAL SPECIFICATIONS 4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS Table 4-8 and Table 4-14 list the AC characteris- tics of the ISA interface. Figure 4-8 ISA Cycle (ref Table ALE AEN LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# ...
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Name Parameter 10d Memory access to 8-bit ISA Slave 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 11 ISACLK2X to IOW# valid 11a Memory access to 16-bit ISA Slave - 2BCLK 11b Memory access to 16-bit ISA Slave - ...
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ELECTRICAL SPECIFICATIONS Name Parameter 24 IOR#, IOW# asserted before SA[19:0] 24o I/O access to 16-bit ISA Slave Standard cycle 24r I/O access to 16-bit ISA Slave Standard cycle 25 MEMR#, MEMW# asserted before next ALE# asserted 25b Memory access to ...
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Name Parameter 41 SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16-bit ISA Slave 41b Memory access to 8-bit ISA Slave 41c I/O access to 16-bit ISA Slave 41d I/O access to 8-bit ISA Slave 42 SA[19:0] SBHE ...
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ELECTRICAL SPECIFICATIONS Name Parameter 64e IOW# negated to write data invalid MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte 64f by ISA Master IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by 64g ISA ...
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LOCAL BUS INTERFACE Figure 4-3 to Figure 4-12 and AC characteristics of the Local Bus interface. HCLK PA[ ] bus T setup CSx# BE#[1:0] PRD# PD[15:0] HCLK PA[ ] bus T setup CSx# BE#[1:0] PRD# PD[15:0] PRDY Table 4-16 ...
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ELECTRICAL SPECIFICATIONS HCLK PA[ ] bus T setup CSx# BE#[1:0] PWR# PD[15:0] HCLK PA[ ] bus T setup CSx# BE#[1:0] PWR# PD[15:0] PRDY 60/111 Figure 4-11. Synchronous Write Cycle T active Figure 4-12. Asynchronous Write Cycle Issue 1.0 - July ...
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The Table 4-15 below refers to Vh, Va, Vs which are the register value for Setup time, Active Time Cycle Memory (FCSx#) Peripheral (IOCSx#) Table 4-16. Local Bus Interface AC Timing Name Parameters HCLK to PA bus HCLK to PD ...
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ELECTRICAL SPECIFICATIONS 4.5.8 PCMCIA INTERFACE Table 4-17 lists the AC characteristics of the PCMCIA interface. Name Parameters t27 Input setup to ISACLK2X t28 Input hold from ISACLK2X t29 ISACLK2X to IORD t30 ISACLK2X to IORW t31 ISACLK2X to AD[25:0] t32 ...
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IDE INTERFACE Figure 4-13, Figure 4-14 and AC characteristics of the IDE interface. CS#,DA[2:0] DIOR#,DIOW# DD[15:0] IORDY CS# REQ ACK# DIOR#,DIOW# DD[15:0] read DD[15:0] write Name Parameters Tsetup DD[15:0] setup to PIOR#/SIOR# falling Thold DD[15:0} hold to PIOR#/SIOR# falling ...
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ELECTRICAL SPECIFICATIONS 4.5.10 VGA INTERFACE Table 4-19 lists the AC characteristics of the VGA interface. Table 4-19. Graphics Adapter (VGA) AC Timing Name Parameter DCLK (input) Cycle Time DCLK (input) High Time DCLK (input) Low Time DCLK (input) Rising Time ...
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VIDEO INPUT PORT Table 4-21 lists the AC characteristics of the VIP interface. Name Parameter VCLK Cycle Time VCLK High Time VCLK Low Time VCLK Rising Time VCLK Falling Time VIN[7:0] setup to VCLK VIN[7:0] hold from VCLK ODD_EVEN ...
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ELECTRICAL SPECIFICATIONS 4.5.13 USB INTERFACE The USB interface integrated into the STPC device is compliant with the USB 1.1 standard. 4.5.14 KEYBOARD & MOUSE INTERFACES Table 4-22 and Table 4-23 characteristics of the Keyboard and Mouse interfaces. Name Parameters Input ...
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JTAG INTERFACE Figure 4-15 and Table 4-21 characteristics of the JTAG interface. T reset TRST TCK TMS,TDI TDO STPC.input STPC.output Name Parameter Treset TRST pulse width Tcycle TCLK period TCLK rising time TCLK falling time Tjset TMS setup time ...
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ELECTRICAL SPECIFICATIONS 4.5.17 INTENSIONNALLY BLANK 68/111 Issue 1.0 - July 24, 2002 ...
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MECHANICAL DATA 5.1. 516-PIN PACKAGE DIMENSION The pin numbering for the STPC 516-pin Plastic BGA package is shown in Figure Figure 5-1. 516-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 516-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 516-pin PBGA Package - PCB Dimensions Symbols Min A 34.80 B 1.22 C 0.60 D 1.57 E 0.15 F 0.05 G 0.75 70/111 ...
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Figure 5-3. 516-pin PBGA Package - Dimensions C Solderball A Table 5-2. 516-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E 0. Solderball after collapse G mm Typ ...
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MECHANICAL DATA 5.2. 516-PIN PACKAGE THERMAL DATA 516-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Signal layers Figure 5-5. Thermal Dissipation Without Heatsink Board Ambient Rca Case Rjc Junction ...
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Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Board Junction Rjb Board Rba Ambient Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC) The PBGA is centred on ...
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MECHANICAL DATA 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. ...
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DESIGN GUIDELINES 6.1. TYPICAL APPLICATIONS The STPC Atlas is well suited for many applications. Some of implementations are described below. 6.1.1. THIN CLIENT A Thin-Client is a terminal running ICA TM or RDP (Microsoft) protocol. The display is computed ...
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DESIGN GUIDELINES 6.1.2. INTERNET TERMINAL The internet terminal described here is an optimized implementation where the STPC Atlas board is integrated into the CRT itself. The advantages are a reduced overall cost and a good image definition. The STPC Atlas ...
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STPC CONFIGURATION The STPC is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. As some trade off are often necessary important analysis of the application ...
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DESIGN GUIDELINES 6.3.1. POWER DECOUPLING An appropriate decoupling of the various STPC power pins is mandatory for optimum behaviour. When insufficient, the integrity of the signals is deteriorated, the stability of the system is reduced and EMC is increased. 6.3.1.1. ...
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SDRAM The STPC provides all the signals for SDRAM control 128 MBytes of main memory are supported. All Banks must be 64 bits wide memory banks are available when using 16Mbit devices. Only up ...
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DESIGN GUIDELINES Figure 6-6. One Memory Banks with 8 Chips (8-bit) MCLKI 10pF MCLKO CY2305 CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] Figure 6-7. Two Memory Banks with 8 Chips (8-bit) MCLKI 22pF MCLKO CY2305 CS1# CS0# MA[12:0] BA[1:0] ...
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For other implementations like 32-bit SDRAM devices, refers to the SDRAM controller signal SDRAM Density Internal Banks DIMM Pin Number ... 123 126 39 122 BA0 (MA11) Address Mapping: 16 Mbit - 2 internal banks STPC I/F BA0 RAS Address ...
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DESIGN GUIDELINES In the case of higher clock load it is recommended to use a zero-delay clock buffer as described in Figure 6-9. This approach is also recommended Figure 6-9. PCI clock routing with zero-delay clock buffer PCICLKI PLL PCICLKO ...
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LOCAL BUS The local bus has all the signals to directly connect flash devices or I/O devices. Figure 6-10. Typical 16-bit boot flash implementation 22 PA[22:1] FCS0# PRD# PWR# 16 PD[15:0] SYSRSTI# STPC Figure 6-10 describes how to connect ...
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DESIGN GUIDELINES 6.3.6. IPC Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. The figure below describes a complete implementation of the IRQ[15:0] time-multiplexing. Timer 0 Keyboard Slave PIC COM2/COM4 COM1/COM3 LPT2 Floppy LPT1 ...
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The figure below describes implementation of the external glue logic for DMA Request time-multiplexing and DMA Acknowledge demultiplexing. Like for the interrupt lines, this Figure 6-12. Typical DMA multiplexing and demultiplexing ISA, Refresh ISA, PIO ISA, FDC ISA, PIO Slave ...
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DESIGN GUIDELINES 6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING Some of the ISA bus signals are dynamically multiplexed to optimize the pin count. Figure 6-13. Typical IDE / ISA Demultiplexing STPC bus / DD[15:0] 6.3.8. BASIC AUDIO USING IDE INTERFACE When ...
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VGA INTERFACE The STPC integrates a voltage reference and video buffers. The amount of external devices is then limited to the minimum as described in the Figure 6-15. All the resistors and capacitors have close as ...
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DESIGN GUIDELINES 6.3.10. USB INTERFACE The STPC integrates a USB host interface with a 2-port Hub. The only external device needed are USBDMNS[0] USBDPLS[0] USBDMNS[1] USBDPLS[1] OC POWERON STPC Note 1; The ESD protection will be adequate for most applications. ...
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KEYBOARD/MOUSE INTERFACE The STPC integrates a PC/AT+ keyboard and PS/2 mouse controller. The only external devices Figure 6-17. Typical Keyboard / Mouse implementation MDATA MCLK KBDATA KBCLK STPC needed are KBMF01SC6. Figure 6-17 implementation using a dual minidin connector. ...
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DESIGN GUIDELINES 6.3.12. PARALLEL PORT INTERFACE The STPC integrates a parallel port where the only external device needed is the ESD protection Figure 6-18. Typical parallel port implementation ACK# BUSY PE SLCT SLCTIN# INIT# ERR# AUTOFD# STROBE# PD[7:0] STPC 90/111 ...
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JTAG INTERFACE The STPC integrates a JTAG interface for scan- chain and on-board testing. The only external Figure 6-19. Typical JTAG implementation TCLK TDO TMS TDI TRST STPC device needed are the pull up resistors. 19 describes a typical ...
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DESIGN GUIDELINES 6.4. PLACE AND ROUTE RECOMMENDATIONS 6.4.1. GENERAL RECOMMENDATIONS Some STPC Interfaces run at high speed and need to be carefully routed or even shielded like: 1) Memory Interface 2) PCI bus 3) Graphics and video interfaces 4) 14 ...
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MEMORY INTERFACE 6.4.3.1. Introduction In order to achieve SDRAM memory interfaces which work at clock frequencies of 90 MHz and above, careful consideration has to be given to the timing of the interface with all the various electrical and ...
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DESIGN GUIDELINES memory clock input (MCLKI) and any other component using the memory individually driven from a low skew clock driver with matched routing lengths. In other words, all Low skew clock driver: MCLKO * No additional 75mm when SDRAM ...
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The maximum skew between pins for this part is 250ps. The important factors for the clock buffer are a consistent drive strength and low skew between the outputs. The delay through the buffer is not important so it does not ...
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DESIGN GUIDELINES Figure 6-25. IBIS Simulation for on-board SDRAM / 90MHz (V) 3 MCLKI MCLKx 2 1 Figure 6-26. Recommended topology for DIMM (IBIS model) Buffer out Buffer out Track impedance= 75 Ohms Trace thickness = 0.72 mil Trace width ...
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Figure 6-27. IBIS Simulation for DIMM / 90MHz (V) 3 MCLKI Buffer output 2 1. 0.8 V Issue 1.0 - July 24, 2002 DESIGN GUIDELINES MCLKx 1.20 ns Time 97/111 ...
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DESIGN GUIDELINES 6.4.4. PCI INTERFACE 6.4.4.1. Introduction In order to achieve a PCI interface which work at clock frequencies up to consideration has to be given to the timing of the interface with all the various electrical and physical constraints ...
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Board Layout Issues The physical layout of the motherboard PCB assumed in this presentation is as shown in 6-29. For the PCI interface, the most critical signal is the clock. Any skew between the clocks at the PCI components ...
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DESIGN GUIDELINES 6.4.5. THERMAL DISSIPATION 6.4.5.1. Power saving Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage ...
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When considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. Figure 6-32. Recommended 1-wire Power/Ground Pad Layout Considering only the central matrix of 36 thermal balls ...
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DESIGN GUIDELINES To avoid solder wicking over to the via pads during soldering important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a diameter of 33 mil for a 25 mil ...
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As the PCB acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. The only limitation is the risk of losing routing channels. Figure 6-36 ...
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DESIGN GUIDELINES Figure 6-37. Recommend signal wiring (top & ground layers) with corresponding heat flow GND 104/111 Power GND Power Issue 1.0 - July 24, 2002 Power/GND balls Internal row Signal balls External row Keep-Out = 6 mils Power/GND balls ...
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DEBUG METHODOLOGY In order to bring a STPC-based board to life with the best efficiency recommended to follow the check-list described in this section. 6.5.1. POWER SUPPLIES In parallel with the assembly process useful to ...
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DESIGN GUIDELINES 6.5.3.2. Boot Flash size The ISA bus supports 8-bit and 16-bit memory devices. In case of a 16-bit boot flash, the signal MEMCS16# must be RMRTCCS# cycle to inform the ISA controller of a 16-bit device. 6.5.3.3. POST ...
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Check: Measure SYSRSTI# of STPC SYSRSTI# 3 (Power Good) Figure 4-3 See Measure HCLK is at selected frequency 5 HCLK 25MHz < HCLK < 66MHz Measure PCICLKO: - maximum is 33MHz by standard - check selected frequency ...
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DESIGN GUIDELINES 6.5.7. 108/111 Issue 1.0 - July 24, 2002 ...
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... ORDERING DATA 7.1. ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID I2: Atlas Core Speed G: 120 MHz H: 133 MHz Memory Speed D: 90 MHz E: 100 MHz Package Y: 516 Overmoulded BGA Temperature Range C: Commercial Tcase = 0 to +85°C I: Industrial Tcase = -40 to +115° Issue 1 ...
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... ORDERING DATA 7.2. AVAILABLE PART NUMBERS Core Frequency Part Number (MHz) 1 STPCI2HEYC 133 STPCI2GDYI 120 Note 1: The STPC Atlas MClock signal can run up to 100MHz reliably, but PCB layout is so critical that the maximum guaranteed speed is 90MHz 110/111 Memory Interface CPU Mode ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...