sy100el15l Micrel Semiconductor, sy100el15l Datasheet

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sy100el15l

Manufacturer Part Number
sy100el15l
Description
Sy100el15l 3.3v 1 4 Clock Distribution Ic
Manufacturer
Micrel Semiconductor
Datasheet

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Micrel
© 1999 Micrel
Synergy™ High-Speed Products
FEATURES
PIN CONFIGURATION/BLOCK DIAGRAM
PIN NAMES
3.3V power supply
50ps output-to-output skew
Low power
Synchronous enable/disable
Multiplexed clock input
75K internal input pull-down resistors
ESD protection of 2000V
Available in 16-pin SOIC package
CLK
SCLK
EN
SEL
V
Q
Pin
BB
0-3
Q
16
1
0
EN
Q
15
2
0
D
Q
SCLK
Q
14
3
1
Differential Clock Inputs
Synchronous Clock Input
Synchronous Enable
Clock Select Input
Reference Output
Differential Clock Outputs
TOP VIEW
CLK
1
Q
13
4
1
SOIC
0
CLK
12
Q
5
2
Function
V
11
Q
BB
6
2
SEL
Q
10
7
3
V
9
8
EE
3.3V 1:4 CLOCK
DISTRIBUTION
1
IC designed explicitly for low skew clock distribution
applications. The device can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used the V
to the CLK input and bypassed to ground via a 0.01 F
capacitor. The V
switching reference for the input of the EL15 under single-
ended input conditions. As a result, this pin can only
source/sink up to 0.5mA of current.
for the distribution of a lower speed scan or test clock
along with the high speed system clock. When LOW (or
left open and pulled LOW by the input pull-down resistor)
the SEL pin will select the differential clock input.
outputs will only be enabled/disabled when they are
already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The internal flip flop is clocked on the falling edge of the
input clock, therefore all associated specification limits
are referenced to the negative edge of the clock input.
will pull down to V
V
* On next negative transition of CLK or SCLK
CC
DESCRIPTION
TRUTH TABLE
The SY100EL15L is a low skew 1:4 clock distribution
The EL15 features a multiplexed clock input to allow
The common enable (EN) is synchronous so that the
When both differential inputs are left open, CLK input
CLK
/2.
H
L
X
X
X
SCLK
X
X
H
X
L
BB
EE
output is designed to act as the
and CLK input will bias around
BB
SEL
H
H
X
L
L
output should be connected
ClockWorks™
EN
H
L
L
L
L
Rev.: A
Issue Date: December 1999
SY100EL15L
ClockWorks™
SY100EL15L
Amendment: /0
L*
Q
H
H
L
L

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sy100el15l Summary of contents

Page 1

... Micrel 3.3V 1:4 CLOCK DISTRIBUTION DESCRIPTION The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal single-ended input used the V to the CLK input and bypassed to ground via a 0 ...

Page 2

... ClockWorks™ SY100EL15L Unit VDC VDC mA C Max. Unit –880 mV –1620 mV — mV –1610 mV –880 mV –1475 mV 150 A — A — – ...

Page 3

... The numbers in the spec table assume a EE (Min)|. Package Operating Type Range Z16-2 Commercial Z16-2 Commercial ClockWorks™ SY100EL15L Max. Unit ps 700 750 750 200 ps 50 — ps — ps — –0.4 –0.4 575 ...

Page 4

... This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc (408) 914-7878 http://www.synergysemi.com http://www.micrel.com FAX WEB © 1999 Micrel Incorporated 4 ClockWorks™ SY100EL15L ...

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