TDA19989 NXP Semiconductors, TDA19989 Datasheet
TDA19989
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TDA19989 Summary of contents
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... General description TDA19989 is a very low power and very small size High-Definition Multimedia Interface (HDMI) v. 1.3a transmitter backward compatible DVI 1.0 and can be connected to any DVI 1.0 and HDMI sink. This device is primarily intended for mobile applications like Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and Ultra-Mobile Personal Computer (UM PC) where size and very low power are mandatory for battery autonomy ...
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... I S-bus AUDIO S/PDIF video RGB COLOR INPUT SPACE FORMATTER YCbCr CONVERTER TDA19989 high-level block diagram Compliance: DVI 1.0 HDMI 1.3a EIA/CEA-861B CEC (HDMI 1.3) SimplayHD HDCP 1.3 Video: xvYCC HDMI 1.3 feature Video formats with a pixel rate up to 150 MHz: RGB YCbCr YCbCr semi-planar ...
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... Digital Still Camera (DSC) Portable Multimedia Player (PMP) Mobile Phone Ultra-Mobile Personal Computer (UM PC) Ordering information Package Name Description TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT962-3 Rev. 01 — 15 February 2010 TDA19989 Version © NXP B.V. 2010. All rights reserved ...
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... VPA[0] to VPA[ CAPTURE VPB[0] to VPB[ VPC[0] to VPC[7] VIDEO PROCESSING (1) The color space converter can be bypassed. The device can handle HDCP based on 1.3 features. Fig 2. TDA19989 Block diagram TDA19989 HDMI PACKET INSERTION INFO FRAME DATA OTP ISLAND MEMORY PACKET KEYS ACR ...
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... HDMI or CEC E8 O negative data channel 0 for TMDS output D8 O positive data channel 0 for TMDS output C8 O negative data channel 1 for TMDS output Rev. 01 — 15 February 2010 TDA19989 001aal266 2 C-bus. In calibration mode © NXP B.V. 2010. All rights reserved ...
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... PLL analog supply voltage (1.8 V), this PLL provides the clock DDA(PLL)(1V8) for the serializer G7 analog supply voltage (1.8 V), is used for parallel-to-serial DDA(1V8) shift register and miscellaneous blocks E5 P core digital supply voltage (1.8 V) DDDC Rev. 01 — 15 February 2010 TDA19989 © NXP B.V. 2010. All rights reserved ...
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... The video data input formats are: TDA19989 is able to output HDMI with the formats: It can also handle audio formats: TDA19989 is also designed to support CEC protocol. For more details about CEC, refer to HDMI 1.3a specification. 7.1 System clock The system clock section has a PLL serializer. ...
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... NXP Semiconductors 7.2 Video input formatter 7.2.1 Description TDA19989 has three video input ports VPA[0] to VPA[7], VPB[0] to VPB[7] and VPC[0] to VPC[7]. TDA19989 can accept any of the following video input modes (see TDA19989 can be set to latch data at either rising or falling edge, or both. 7.2.2 Internal assignment The aim of the video input processor is to internally map the incoming data to the corresponding mode, which can be handled by the video processing ...
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... R[7] Cr[7] R[6] Cr[6] R[5] Cr[5] R[4] Cr[4] R[3] Cr[3] R[2] Cr[2] R[1] Cr[1] R[0] Cr[0] 2 C-bus registers VIP_CNTRL_0, VIP_CNTRL_1 and VIP_CNTRL_2 (page Rev. 01 — 15 February 2010 TDA19989 YCbCr YCbCr semi-planar ITU656 CbCr[11] CbCr[10] CbCr[9] CbCr[8] CbCr[7] CbCr[6] CbCr[5] CbCr[4] CbCr[3] CbCr[2] CbCr[1] CbCr[0] Table 4 shows the behavior © NXP B.V. 2010. All rights reserved. ...
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... SWAP_D[2:0] is used to map incoming video port to the internal port VP[11:8]. • SWAP_E[2:0] is used to map incoming video port to the internal port VP[7:4]. • SWAP_F[2:0] is used to map incoming video port to the internal port VP[3:0]. Rev. 01 — 15 February 2010 TDA19989 YCbCr YCbCr semi-planar ITU656 Y [11] ...
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... SWAP_E[2: MIRR_F = 1 SWAP_F[2: When input ports are not used possible to deactivate them via the I appropriate set of registers ENA_VP_0, ENA_VP_1 and ENA_VP_2 on page 00h. TDA19989_1 Preliminary data sheet www.DataSheet.in HDMI 1.3 transmitter with HDCP and CEC support TDA19989 input/output capability Internal port VP[23] VP[22] VP[21] VP[20] VP[19] VP[18] VP[17] ...
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Input format mappings Table 6 gives more information concerning input format supported. Table ...
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... Pin YCbCr Pin YCbCr VPB[0] Y[0] VPC[0] Cr[0] VPB[1] Y[1] VPC[1] Cr[1] VPB[2] Y[2] VPC[2] Cr[2] VPB[3] Y[3] VPC[3] Cr[3] VPB[4] Y[4] VPC[4] Cr[4] VPB[5] Y[5] VPC[5] Cr[5] VPB[6] Y[6] VPC[6] Cr[6] VPB[7] Y[7] VPC[7] Cr[7] Rev. 01 — 15 February 2010 TDA19989 Control RGB Pin R[0] HSYNC/HREF R[1] VSYNC/VREF R[2] DE/FREF R[3] R[4] R[5] R[6] R[7] [7:0] ... B [7:0] B [7:0] xxx xxx [7:0] ... G [7:0] G [7:0] xxx xxx [7:0] ... R [7:0] R [7:0] ...
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... Cr[3] Y [3] VPB[3] Cb[ VPB[4] Cb[ VPB[5] Cb[ VPB[6] Cb[10] Y [10 VPB[7] Cb[11] Y [11 [11:0] Y [11:0] Cr [11: Rev. 01 — 15 February 2010 TDA19989 [7:0] ... Cb [7: xxx xxx Y [7:0] ... Y [7:0] Y [7:0] 3 xxx xxx [7:0] ... Cr [7:0] Cr [7:0] 3 xxx xxx Control Pin Cr[4] Y [4] HSYNC/HREF used 1 Cr[5] Y [5] VSYNC/VREF used 1 Cr[6] Y [6] DE/FREF ...
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... Y [2] VPB[2] Cb[ [3] VPB[3] Cb[ VPB[4] Cb[ VPB[5] Cb[ VPB[6] Cb[10] Y [10 VPB[7] Cb[11] Y [11] 0 Rev. 01 — 15 February 2010 TDA19989 Control Pin YCbCr Cr[4] Y [4] HSYNC/HREF used 1 Cr[5] Y [5] VSYNC/VREF used 1 Cr[6] Y [6] DE/FREF used 1 Cr[7] Y [7] 1 Cr[8] Y [8] 1 Cr[9] Y [9] 1 Cr[10] Y [10] ...
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... Y [ VPB[4] Cb[ VPB[5] Cb[ VPB[6] Cb[10] Y [10 VPB[7] Cb[11] Y [11] 0 [11:0] Y [11:0] Cr [11:0] Y [11: Rev. 01 — 15 February 2010 TDA19989 ... Cr [11:0] Y [1:0] xxx xxx Control Pin YCbCr Cr[4] Y [4] HSYNC/HREF not used 1 Cr[5] Y [5] VSYNC/VREF not used 1 Cr[6] Y [6] DE/FREF not used 1 Cr[7] Y [7] 1 Cr[8] Y [8] ...
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... Y [8] VPC[4] Cb[ VPB[5] Y [9] Y [9] VPC[5] Cb[ VPB[6] Y [10] Y [10] VPC[6] Cb[10 VPB[7] Y [11] Y [11] VPC[7] Cb[11 Rev. 01 — 15 February 2010 TDA19989 Control Pin YCbCr Cr[4] HSYNC/HREF used Cr[5] VSYNC/VREF used Cr[6] DE/FREF used Cr[7] Cr[8] Cr[9] Cr[10] Cr[11] Y [11:0] Y [11:0] ... [11:0] Cr [11:0] ... 4 4 001aai449 Control Pin YCbCr ...
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... Input and output video format Due to the flexible video input formatter, TDA19989 can accept a large range of input formats. This flexibility allows TDA19989 to be compatible with the maximum possible number of MPEG decoders. Moreover, these input formats may be changed in many ways (color space converter, upsampler, downsampler) before it is transmitted across the HDMI link ...
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... This block works only with YCbCr input format; the filters downsample the Cb and Cr signals by a factor delay is added on the Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the Cb-Cr channel. 7.8 Audio input format TDA19989 is compatible with the following audio features described in the HDMI 1.3 specification: TDA19989_1 Preliminary data sheet www ...
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... Digital, DTS, AC3 etc.) layout 1. Only one S/PDIF input can be used at the same time. The selection is done by register. TDA19989 is able to recover the original clock from the S/PDIF signal (no need of external clock). In addition, it can also use an external clock to decode the S/PDIF signal. ...
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... Right justified format. 2 S-bus formats 2 S-bus input interface can receive up to 24-bit wide audio samples via the serial data , only 16-bit audio-samples can be received. In this case, the Rev. 01 — 15 February 2010 TDA19989 LEFT CHANNEL RIGHT CHANNEL LEFT CHANNEL RIGHT CHANNEL (n) (n) (n+1) LSB ...
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... TDA19989 HDMI and CEC cores can be independently powered down by the I register. In Standby mode all activities are reduced by switching off all PLLs, HDMI and CEC cores and disconnecting the biasing structure of the output stage. TDA19989 has a very low power consumption, which is suitable for portable applications. ...
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... The hot plug detect (HPD) pin input tolerant. The HPD signal, when asserted, tells the transmitter that the receiver is connected. When changing from LOW-to-HIGH, TDA19989 has to read the EDID of the receiver in order to select the video format that the receiver can handle. ...
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... HDMI 1.3 transmitter with HDCP and CEC support HDMI cable Vinp_rxs 35 kΩ Vinn_rxs 35 kΩ I_transmit Receiver sensitivity detection is switched off), the RxSense generates an interrupt inside TDA19989, changing the CC Table Receiver detection according to averaged terminal voltage bit RXS_FIL: receiver powered on 1 undefined 0 Rev. 01 — ...
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... I 7.11.1.1 Repeater function TDA19989 can be used in a repeater device according to the HDCP specification, Rev 1.3. TDA19989 is able to store the KSV list of a maximum of 127 devices in a register memory. 7.11.1.2 SHA-1 To deal with repeater, a SHA-1 calculation is performed by the transmitter and by the downstream repeater. For security purposes and in order to relieve the microcontroller, the SHA-1 has been implemented within TDA19989 ...
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... Non successful calibration will lead to CEC signal not matching timings specification consequence, CEC will not be functional. 7.12.3 CEC interrupt Pin INT is used by TDA19989 to warn the host processor that HDMI or CEC events (CEC message is available to read) have occurred. Software interrupt status register reads determine which block between HDMI or CEC has raised the interruption before processing it ...
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... NXP Semiconductors 7.12.4 Power-On Reset (POR) After power-up, TDA19989 is activated by internal reset from POR module. This is used to set TDA19989 to a known state. 7.12.5 Repeater function TDA19989 can be used in a repeater device according to HDMI 1.3a. 7.13 HDMI core 7.13.1 Output TMDS buffers 7.13.1.1 Digitally controlled signal amplitude The TMDS signal output peak-to-peak voltage (Vswing) is programmable by the software ...
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... The block can be read by the system microcontroller to determine the supported video and audio format of the downstream site. Remark: When the block is read by TDA19989, it generates an interrupt to warn the main processor that the chip is ready to transmit the content. Once the content is read out by the main processor, it can allow other blocks to be read if required ...
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... Table 22. CEC core address A6 0 For read access, the master writes the address of TDA19989 HDMI or CEC core, and the subaddress to access the specific register and then the data. Fig 17. I 8.2 Memory page management The I between pages is made with common register CURPAGE_ADR only necessary to write in this register once to change the current page ...
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... Slaves can then hold the CSCL line LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer; see Clock stretching must be supported by I TDA19989 is used. If CEC feature of TDA19989 is not used, I need to support clock stretching. 9. Input format In been mapped to Y (YCbCr space)/G (RGB space) and VPC has been mapped to Cr (YCbCr space)/R (RGB space) ...
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... VPC[3] Cr[3]/R[3] VPC[4] Cr[4]/R[4] VPC[5] Cr[5]/R[5] VPC[6] Cr[6]/R[6] VPC[7] Cr[7]/R[7] 9.1 Timing parameters for video supported TDA19989 supports all EIA/CEA-861B standards and ATSC video input formats. Table 24. Timing parameters for EIA/CEA-861B EIA/CEA-861b Format Video code 59.94 Hz systems 640 × 480p 1 (VGA) 720 × 480p 2, 3 1280 × 720p 4 1920 × ...
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... V frequency H total V total (Hz) 30.000 3300 750 29.970 3300 750 25.000 3960 750 23.976 4125 750 Rev. 01 — 15 February 2010 TDA19989 H frequency Pixel Pixel (kHz) frequency repetition (MHz) [1] 15.750 54.054 4 [1] 15.750 54.054 4 [1] 15.750 54.054 4 31.500 54.054 2 67 ...
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... NXP Semiconductors 9.2 Timing parameters for PC standards supported TDA19989 can support all major PC Standards up to 150 MHz. Table 26. Timing parameters for PC standards below 150 MHz Standard Format 640 × 350p 640 × 400p 720 × 400p 640 × 480p 0.31M3 VGA 640 × 480p 640 × ...
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... Conditions EIA/JESD22-A114 (HBM) EIA/JESD22-C101-C (FCDM) Conditions in free air; JEDEC 4L board Rev. 01 — 15 February 2010 TDA19989 H frequency Pixel frequency Pixel (kHz) (MHz) repetition 64.744 101.000 - 65.317 121.750 - 55.469 88.750 - 55.935 106.500 - 70 ...
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... Preliminary data sheet www.DataSheet.in HDMI 1.3 transmitter with HDCP and CEC support Conditions PLL analog and serializer I = DDA(sum)(1V8 DDA(TMDS)(1V8) DDA(1V8) Sleep mode with CEC Sleep mode without CEC Standby mode Rev. 01 — 15 February 2010 TDA19989 Min Typ Max Unit [1] 1.7 1.8 1.9 V 1.7 1.8 1.9 V 1.7 1.8 1 ...
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... HDMI 1.3 transmitter with HDCP and CEC support Conditions - - - - - - = 10 pF [1] 2 C-bus input/output pins CSCL, CSDA = 10 kΩ ± EXT_SWING 2 C-bus specification version 2.1 (document order number 9398 393 40011). Rev. 01 — 15 February 2010 TDA19989 Min Typ Max 0 - 0.75 1 − − 4 ...
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... Figure 18 and 19 positive edge CEC [2] Standard mode [2] Standard mode Fast mode CEC the TMDS link ). 2 C-bus specification version 2.1 (document order number 9398 393 40011). Rev. 01 — 15 February 2010 TDA19989 Min Typ Max - - 148 ...
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... VCLK VPA[0] to VPA[7] VPB[0] to VPB[7] VPC[0] to VPC[7] DE, HSYNC, VSYNC t su(D) data is not allowed to change in this period data can change to meet the minimum set-up and hold time requirement Rev. 01 — 15 February 2010 TDA19989 EDGE = su(D) h(D) EDGE = su(D) h(D) ...
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... Transmitter connection with external world Figure 20 be part of a repeater application as described in “HDMI specification 1.3a”. Fig 20. Connecting TDA19989 transmitter using external clock source Fig 21. Connecting TDA19989 transmitter using internal FRO for CEC TDA19989_1 Preliminary data sheet www.DataSheet.in HDMI 1.3 transmitter with HDCP and CEC support ...
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... 0.80 0.35 4.6 4.6 0.70 0.30 4.5 4.5 0.5 3.5 3.5 0.65 0.25 4.4 4.4 REFERENCES JEDEC JEITA - - - - - - Rev. 01 — 15 February 2010 TDA19989 detail 0.15 0.05 0.08 0.1 EUROPEAN PROJECTION © NXP B.V. 2010. All rights reserved. SOT962-3 ISSUE DATE 08-05-26 08-06- ...
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... Hot Plug Detection Horizontal REFerence Horizontal SYNChronization Least Significant Bit Low Voltage Complementary Metal-Oxide Semiconductor Moving Picture Experts Group Most Significant Bit One Time Programming Personal Computer Printed Circuit Board Rev. 01 — 15 February 2010 TDA19989 © NXP B.V. 2010. All rights reserved ...
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... Ultra Extended Graphics Array Vertical Horizontal REFerence Vertical REFerence Vertical SYNChronization Y = luminance Chroma component blue Chroma component red Word Select Release date Data sheet status 20100215 Preliminary data sheet Rev. 01 — 15 February 2010 TDA19989 Change notice Supersedes - - © NXP B.V. 2010. All rights reserved ...
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... In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Rev. 01 — 15 February 2010 TDA19989 © NXP B.V. 2010. All rights reserved ...
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... Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 15 February 2010 TDA19989 © NXP B.V. 2010. All rights reserved ...
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... Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3. Internal assignment . . . . . . . . . . . . . . . . . . . . . .8 Table 4. Video input swap to VP[23:20 .10 Table 5. TDA19989 input/output capability . . . . . . . . . . 11 Table 6. Inputs of video input formatter . . . . . . . . . . . . .12 Table 7. RGB (3 ¥ 8-bit) external synchronization input (rising edge) mapping . . . . . . . . . . . . . . . . . . .13 Table 8. YCbCr ¥ 8-bit) external synchronization input (rising edge) mapping . . . . . . . . . . . . . . .13 Table 9 ...
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... NXP Semiconductors 21. Figures Fig 1. TDA19989 high-level block diagram . . . . . . . . . . .2 Fig 2. TDA19989 Block diagram . . . . . . . . . . . . . . . . . . .4 Fig 3. Pin configuration (TFBGA64 Fig 4. Internal assignment of VP[23:0 Fig 5. Pixel encoding RGB external synchronization input (rising edge .13 Fig 6. Pixel encoding YCbCr external synchronization input (rising edge .14 Fig 7. ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 February 2010 Document identifier: TDA19989_1 All rights reserved. ...