TDA7439 STMicroelectronics, TDA7439 Datasheet

IC PROCESSOR AUDIO DGTL 30-SDIP

TDA7439

Manufacturer Part Number
TDA7439
Description
IC PROCESSOR AUDIO DGTL 30-SDIP
Manufacturer
STMicroelectronics
Type
Audio Processorr
Datasheet

Specifications of TDA7439

Applications
Automotive Systems
Mounting Type
Through Hole
Package / Case
30-SDIP (0.400", 10.16mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8866-5
TDA7439

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Features
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Description
The TDA7439 is a volume, tone (bass, mid-range
and treble) and balance (left/right) processor for
Table 1. Device summary
March 2008
TDA7439
Input multiplexer
– four stereo inputs
– selectable input gain for optimal adaptation
Single stereo output
Treble, mid-range and bass control in 2-dB
steps
Volume control in 1-dB steps
Two speaker attenuators:
– two independent speaker controls in 1-dB
– independent mute function
All functions are programmable via serial bus.
to different sources
steps for balance facility
Order code
Three-band digitally-controlled audio processor
SDIP30
Package
Rev 11
high-quality audio applications in car-radio and
Hi-Fi systems. Selectable input gain is provided.
All the functions are controlled by serial bus.
The AC signal setting is obtained by resistor
networks and switches combined with operational
amplifiers.
The TDA7439 employs BIPOLAR/CMOS
technology to provide low distortion, low noise
and DC stepping.
Tube
SDIP30
Packaging
TDA7439
www.st.com
1/23
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Related parts for TDA7439

TDA7439 Summary of contents

Page 1

... All functions are programmable via serial bus. Description The TDA7439 is a volume, tone (bass, mid-range and treble) and balance (left/right) processor for Table 1. Device summary Order code TDA7439 March 2008 ...

Page 2

... I C bus transmission examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 No address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Address incrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus addresses and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 Chip address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Sub-address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 Data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 Chip input/output circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/23 Bass, mid-range stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Treble stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TDA7439 ...

Page 3

... TDA7439 1 Block diagram and pin out Figure 1. Block diagram 11 L-IN1 100K 12 L-IN2 100K 13 L-IN3 100K 14 L-IN4 100K 10 R-IN1 100K 9 R-IN2 100K 8 R-IN3 100K 7 R-IN4 100K Figure 2. Pin connections MUXOUTL INL TREBLE( VOLUME TREBLE 0/30dB I 2dB STEP G VOLUME TREBLE INPUT MULTIPLEXER + GAIN ...

Page 4

... Test condition Value 10 -55 to 150 Value 85 Min Typ Max 6 9 10.2 2 0.01 0.1 106 -47 -14 +14 -14 +14 -14 +14 -79 100 Figure 600 Ω, all controls flat ( dB), g Min Typ Max TDA7439 Unit V °C °C Unit °C/W Unit V V RMS % amb Unit ...

Page 5

... TDA7439 Table 5. Electrical characteristics (continued) Symbol Input stage R Input resistance IN V Clipping level CL S Input separation IN G Minimum input gain in_min G Maximum input gain in_max G Step resolution step Volume control R Volume control input resistance i C Volume control range range A Max. attenuation ...

Page 6

... For bass, mid-range and treble response: the center frequency and the response quality can be set by the external circuitry. 6/23 Parameter Test condition - - Adjacent attenuation steps d = 0.3% All gains = 0 dB kHz flat - - All gains 0 dB RMS RMS 0 1 TDA7439 Min Typ Max Unit 0.5 1 1.5 dB -1 100 dB 2.1 2.6 Vrms 2 kΩ Ω ...

Page 7

... TDA7439 Figure 3. Test circuit L-IN1 0.47µF L-IN2 0.47µF L-IN3 0.47µF L-IN4 0.47µF R-IN1 0.47µF R-IN2 0.47µF R-IN3 0.47µF R-IN4 0.47µF 5.6nF 2.2µF MUXOUTL INL TREBLE( 100K 12 100K 13 G VOLUME TREBLE 100K 14 100K ...

Page 8

... Both control blocks have a step resolution of 1 dB. This very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7439 audio processor provides 3 bands of tone control (bass, mid-range and treble). 3.1 Tone control 3 ...

Page 9

... TDA7439 Transposing and solving for the external component values we get: = ----------------------------------------- - C1 2 π ⋅ ⋅ ----------------------------- - C2 – --------------------------------------------------------------------- - R2 2 π ⋅ ⋅ 3.1.2 Treble stage The treble stage is a high-pass filter whose time constant is fixed by an internal resistor (25 kΩ typically) and an external capacitor connected between treble pins and ground. ...

Page 10

... Application suggestions Figure 7. Channel separation vs frequency Figure 9. Mid-range filter response Figure 11. Typical tone response 10/23 Figure 8. Bass filter response Figure 10. Treble filter response TDA7439 ...

Page 11

... TDA7439 bus interface Data transmission from the microprocessor to the TDA7439 and vice versa takes place through the 2-wire I Pull-up resistors to the positive supply voltage must be used (there are no internal pull-ups). 4.1 Data validity The data on the SDA line must be stable during the high period of the clock as shown in Figure 12 ...

Page 12

... SDA Start 4.6 Interface protocol The interface protocol comprises: " a start condition (S) " a chip-address byte, containing the TDA7439 address " a sub-address byte including an auto address-increment bit " a sequence of data bytes (N bytes + acknowledge) " a stop condition (P). Figure 15. SDA addressing and data CHIP ADDRESS ...

Page 13

... D96AU421 5.2 Address incrementing The TDA7439 receives a start condition followed by the correct chip address, then a sub address with the for address incrementing; now loop condition with an automatic increase of the sub address up to D[3:0] = 0x7. That is, the data for sub addresses from D[3:0] = 1000 (binary) to 1111 are ignored. ...

Page 14

... C bus addresses and data bus addresses and data 6.1 Chip address byte The TDA7439 chip address is 0x88. 6.2 Sub-address byte The function is selected by the 4-bit sub address as given in not used and bit D4 selects address incrementing ( single data byte (B = 0). Table 7. Function selection: sub-address byte ...

Page 15

... TDA7439 Table 9. Input gain value (sub address 0x1) MSB Table 10. Volume value (sub address 0x2) MSB bus addresses and data LSB Input gain 2-dB steps LSB Volume 1-dB steps - - - - MUTE 15/23 ...

Page 16

... I C bus addresses and data Table 11. Bass gain value (sub address 0x3) MSB Table 12. Mid-range gain value (sub address 0x4) MSB 16/ LSB Bass gain 2-dB steps - - - LSB Mid-range gain 2-dB steps - - - TDA7439 ...

Page 17

... TDA7439 Table 13. Treble gain value (sub address 0x5) MSB Table 14. Speaker attenuation value (sub address 0x6, 0x7) MSB bus addresses and data LSB Treble gain 2-dB steps - - - - LSB Speaker attenuation 1-dB steps 17/23 ...

Page 18

... I C bus addresses and data Table 14. Speaker attenuation value (sub address 0x6, 0x7) (continued) MSB 18/ LSB Speaker attenuation 1-dB steps MUTE TDA7439 ...

Page 19

... TDA7439 7 Chip input/output circuits Figure 18. Pin 2 V CREF Figure 20. Pins 10, 11, 12, 13, 14 Figure 21. Pins 15 100K V REF Figure 22. Pins 20 MOUT(L) MOUT(R) Figure 19. Pins 20K 20K D96AU430 20µA D96AU425 Figure 23. Pins 19, 26 20µA 25K D96AU431 Chip input/output circuits ROUT LOUT 20µA D96AU434 MIXOUT ...

Page 20

... V S TREBLE(L) TREBLE(R) Figure 28. Pin 1 SDA 20/23 Figure 25. Pins 22, 24 20µA 44K BOUT(L) BOUT(R) D96AU428 Figure 27. Pin 30 20µA 50K D96AU433 Figure 29. Pins 16, 18 20µA D96AU423 V S 20µA 44K D96AU429 20µA SCL D96AU424 V S 20µA INL INR 33K D96AU427 V REF TDA7439 ...

Page 21

... TDA7439 8 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 22

... Revision history 9 Revision history Table 15. Document revision history Date Jan-2004 Jun-2004 21-Mar-2008 22/23 Revision 9 Initial release in EDOCS DMS 10 Modified presentation Updated titles to Figure 9 11 Minor updates to presentation TDA7439 Changes and Figure 10 ...

Page 23

... TDA7439 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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