TDA9981B NXP Semiconductors, TDA9981B Datasheet
TDA9981B
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TDA9981B Summary of contents
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... Rev. 01 — 4 July 2008 1. General description The TDA9981B is an HDMI transmitter (which also supports DVI) that enables a 3 RGB or YCbCr video stream (with a pixel rate up to 150 MHz for the TDA9981BHL/15 version the additional information required by all the HDMI 1.2a standards. ...
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... V DDD(3V3) Typical values are measured DDC(1V8) Symbol TDA9981BHL/8 and TDA9981BHL/15 V DDA(FRO_3V3) V DDA(PLL_3V3) V DDD(3V3) V DDH(3V3) V DDC(1V8) T amb TDA9981BHL/ MHz f clk(max) P cons P tot P pd TDA9981BHL/15 150 MHz f clk(max) P cons P tot P pd [1] Worst case: video input format: 720p (RGB embedded sync), video output format: 720p (YCbCr ...
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... Survey of type numbers Sampling frequency (MHz) 81 150 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Version SOT315-1 Application customer specific version customer specific version © NXP B.V. 2008. All rights reserved ...
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... TO ( 12-bit or 1 12-bit 15, 60, 25, 31 SSC SSA(FRO_3V3) SSA(PLL_3V3) SSH SSA(PLL_1V8 DDC_SCL DDC-BUS 19 DDC_SDA 17 IRQ INT GENERATION 27 TXC+ 26 TXC 30 TX0+ 29 TX0 HDMI SERIALIZER 33 TX1+ 32 TX1 36 TX2+ 35 TX2 TDA9981B 21 24 001aai221 TM EXT_SWING ...
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... I audio port 7 input; auxiliary (AUX audio port 6 input; S/PDIF stream 6 I audio port 5 input; optional master clock MCLK for S/PDIF Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter 60 V SSC 59 V DDC(1V8) 58 VPB[6] 57 ...
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... I C-bus slave address input 1; bit C-bus slave address input 0; bit hard reset input; active LOW Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter 2 S-bus port 3 2 S-bus port 2 2 S-bus port 1 2 S-bus port 0 2 S-bus ...
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... I video port A input bit video port A input bit video port A input bit video data enable input or field reference input Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter © NXP B.V. 2008. All rights reserved ...
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... The TDA9981B has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0]. The TDA9981B can reallocate and swap each of the 3 input channel ports by inverting the bus and swapping each port. The TDA9981B can be set to latch data at either the rising or falling edge or both. The video input formats accept (see • ...
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Table 5. Inputs of video input formatter Color Format Channels Sync space RGB 8-bit external external embedded embedded YCbCr 8-bit ...
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... RGB Pin G[0] VPC[0] G[1] VPC[1] G[2] VPC[2] G[3] VPC[3] G[4] VPC[4] G[5] VPC[5] G[6] VPC[6] G[7] VPC[ Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control RGB Pin R[0] HSYNC/HREF R[1] VSYNC/VREF R[2] DE/FREF R[3] R[4] R[5] R[6] R[7] B3 ... Bxxx Bxxx G3 ... Gxxx Gxxx R3 ... Rxxx Rxxx © NXP B.V. 2008. All rights reserved. ...
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... Pin Y[0] VPC[0] Y[1] VPC[1] Y[2] VPC[2] Y[3] VPC[3] Y[4] VPC[4] Y[5] VPC[5] Y[6] VPC[6] Y[7] VPC[7] Cb0 Cb1 Cb2 Cr0 Cr1 Cr2 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control YCbCr Pin CR[0] HSYNC/HREF CR[1] VSYNC/VREF CR[2] DE/FREF CR[3] CR[4] CR[5] CR[6] CR[7] Cb3 ... Cbxxx C Y3 ... Yxxx Yxxx Cr3 ... Crxxx Crxxx © ...
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... YCbCr (ITU656-like) Y1[0] VPB[0] CB[4] Y0[4] Y1[1] VPB[1] CB[5] Y0[5] Y1[2] VPB[2] CB[6] Y0[6] Y1[3] VPB[3] CB[7] Y0[7] - VPB[4] CB[8] Y0[8] - VPB[5] CB[9] Y0[9] - VPB[6] CB[10] Y0[10] CR[10] Y1[10] - VPB[7] CB[11] Y0[11] CR[11] Y1[11] Cb0 Y0 Cr0 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control Pin CR[4] Y1[4] HSYNC/HREF used CR[5] Y1[5] VSYNC/VREF CR[6] Y1[6] DE/FREF CR[7] Y1[7] CR[8] Y1[8] CR[9] Y1[9] Y1 ... Crxxx Yxxx © NXP B.V. 2008. All rights reserved. YCbCr used used ...
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... VPB[0] CB[4] Y0[4] Y1[1] VPB[1] CB[5] Y0[5] Y1[2] VPB[2] CB[6] Y0[6] Y1[3] VPB[3] CB[7] Y0[7] - VPB[4] CB[8] Y0[8] - VPB[5] CB[9] Y0[9] - VPB[6] CB[10] Y0[10] - VPB[7] CB[11] Y0[11] Cb0 Y0 Cr0 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control Pin CR[4] Y1[4] HSYNC/HREF CR[5] Y1[5] VSYNC/VREF CR[6] Y1[6] DE/FREF CR[7] Y1[7] CR[8] Y1[8] CR[9] Y1[9] CR[10] Y1[10] CR[11] Y1[11] Y1 ... Crxxx Yxxx © NXP B.V. 2008. All rights reserved. YCbCr used used used 001aai432 ...
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... VPB[2] CB[6] Y0[6] CR[6] Y1[3] VPB[3] CB[7] Y0[7] CR[7] - VPB[4] CB[8] Y0[8] CR[8] - VPB[5] CB[9] Y0[9] CR[9] - VPB[6] CB[10] Y0[10] CR[10] - VPB[7] CB[11] Y0[11] CR[11] Y0 Cr0 Y1 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control Pin YCbCr Y1[4] HSYNC/HREF not used Y1[5] VSYNC/VREF not used Y1[6] DE/FREF not used Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] ... Crxxx Yxxx 001aai436 © NXP B.V. 2008. All rights reserved ...
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... VPB[2] CB[6] Y0[6] CR[6] Y1[3] VPB[3] CB[7] Y0[7] CR[7] - VPB[4] CB[8] Y0[8] CR[8] - VPB[5] CB[9] Y0[9] CR[9] - VPB[6] CB[10] Y0[10] CR[10] - VPB[7] CB[11] Y0[11] CR[11] Y0 Cr0 Y1 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control Pin YCbCr Y1[4] HSYNC/HREF not used Y1[5] VSYNC/VREF not used Y1[6] DE/FREF not used Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] ... Crxxx Yxxx 001aai435 © NXP B.V. 2008. All rights reserved ...
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... VPB[2] Y0[6] Y1[6] VPC[2] VPB[3] Y0[7] Y1[7] VPC[3] VPB[4] Y0[8] Y1[8] VPC[4] VPB[5] Y0[9] Y1[9] VPC[5] VPB[6] Y0[10] Y1[10] VPC[6] VPB[7] Y0[11] Y1[11] VPC[ Cb0 Cr0 Cb2 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control YCbCr Pin semi-planar CB[4] CR[4] HSYNC/HREF CB[5] CR[5] VSYNC/VREF CB[6] CR[6] DE/FREF CB[7] CR[7] CB[8] CR[8] CB[9] CR[9] CB[10] CR[10] CB[11] CR[11 Cr2 Cb4 Cr4 © NXP B.V. 2008. All rights reserved. ...
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... VPB[2] Y0[6] Y1[6] VPC[2] VPB[3] Y0[7] Y1[7] VPC[3] VPB[4] Y0[8] Y1[8] VPC[4] VPB[5] Y0[9] Y1[9] VPC[5] VPB[6] Y0[10] Y1[10] VPC[6] VPB[7] Y0[11] Y1[11] VPC[ Cr0 Cb2 Cr2 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Control YCbCr Pin semi-planar CB[4] CR[4] HSYNC/HREF CB[5] CR[5] VSYNC/VREF CB[6] CR[6] DE/FREF CB[7] CR[7] CB[8] CR[8] CB[9] CR[9] CB[10] CR[10] CB[11] CR[11 ... Cb4 Cr4 ... © NXP B.V. 2008. All rights reserved. ...
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... Input and output video format Due to the flexible video input formatter, the TDA9981B can accept a large range of input formats. This flexibility allows the TDA9981B to be compatible with the maximum possible number of MPEG decoders. Moreover, these input formats may be changed in many ways (color space converter, upsampler and downsampler transmitted across the HDMI link ...
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... AP7 ACLK 8.9 S/PDIF The audio port AP6 is used for the S/PDIF feature. In this format the TDA9981B supports 2-channel uncompressed PCM data (IEC 60958) layout 0 or compressed bit stream multichannels (Dolby Digital, DTS, AC-3, etc.) layout 1. The TDA9981B is able to recover the original clock from the S/PDIF signal (no need for an external clock). In addition it can also use an external clock (MCLK) to decode the S/PDIF signal ...
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... RxSense). These interrupts are maskable. Hot plug or unplug detect: pin HPD is the hot plug detection pin input tolerant. 8.13 Initialization Hard reset: after power-up, the TDA9981B is activated by a hard reset via pin RST_N. However, the TDA9981B has a power-on reset. TDA9981B_1 ...
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... CEA EDID timing extension. If the 24-bit IEEE registration identifier contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device will be treated as a DVI device. However, the TDA9981B does not have direct access to that information since E-EDID is read by an external microprocessor through the TDA9981B I 8 ...
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... The I TDA9981B_1 Product data sheet TRANSMITTER switched off), the RxSense generates an interrupt inside the TDA9981B C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode 2 C-bus device address are externally selected by pins A0 and A1. 2 C-bus device address is given in ...
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... NXP Semiconductors For read access, the master writes the address of the TDA9981B, the subaddress to access the specific register and then the data. Fig 13. I 10. Limiting values Table 18. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DD(3V3) ...
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... DDA(FRO_3V3) V PLL 3.3 V analog supply voltage DDA(PLL_3V3) V digital supply voltage (3.3 V) DDD(3V3) V HDMI supply voltage (3.3 V) DDH(3V3) V core supply voltage (1.8 V) DDC(1V8) TDA9981BHL/ MHz I free running oscillator 3.3 V analog supply current DDA(FRO_3V3) I PLL 3.3 V analog supply current DDA(PLL_3V3) I digital supply current (3.3 V) DDD(3V3) I HDMI supply current (3.3 V) DDH(3V3) I core supply current (1 ...
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... PP amb = DDA(FRO_3V3) DDA(PLL_3V3) DDH(3V3) Conditions single output; R ext (1 % tolerance) with test load and operating condition as in HDMI 1.2a specification Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter = 3.6 V; DDD(3V3 3 DDD(3V3) DDC(1V8) Min Typ - - 2.0 - ...
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... amb = DDA(FRO_3V3) DDA(PLL_3V3) DDH(3V3) Conditions TDA9981BHL/8 TDA9981BHL/15 standard mode standard mode fast mode TDA9981BHL/8 TDA9981BHL/15 TDA9981BHL/8 TDA9981BHL/15 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter = 3.6 V; DDD(3V3 3 1 DDD(3V3) DDC(1V8) Min Typ Figure ...
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... VPA has been mapped to CB (YUV space)/B (RGB space), VPB has YUV [1] [ (semi-planar) CB[0] Y0[0] Y1[0] CB[1] Y0[1] Y1[1] CB[2] Y0[2] Y1[2] CB[3] Y0[3] Y1[3] CB[4] CB[0] CR[0] CB[5] CB[1] CR[1] CB[6] CB[2] CR[2] CB[7] CB[3] CR[3] Y[0] Y0[4] Y1[4] Y[1] Y0[5] Y1[5] Y[2] Y0[6] Y1[6] Y[3] Y0[7] Y1[7] Y[4] Y0[8] Y1[8] Y[5] Y0[9] Y1[9] Y[6] Y0[10] Y1[10] Y[7] Y0[11] Y1[11] CR[0] CB[4] CR[4] CR[1] CB[5] CR[5] CR[2] CB[6] CR[6] CR[3] CB[7] CR[7] CR[4] CB[8] CR[8] CR[5] CB[9] CR[9] CR[6] CB[10] CR[10] CR[7] CB[11] CR[11] Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter [3] [ (ITU656-like) CB[0] Y0[0] CR[0] Y1[0] CB[1] Y0[1] CR[1] Y1[1] CB[2] Y0[2] CR[2] Y1[2] CB[3] Y0[3] CR[3] Y1[ CB[4] Y0[4] CR[4] Y1[4] CB[5] Y0[5] CR[5] Y1[5] CB[6] Y0[6] CR[6] Y1[6] CB[7] Y0[7] CR[7] Y1[7] CB[8] Y0[8] CR[8] Y1[8] CB[9] Y0[9] CR[9] Y1[9] CB[10] Y0[10] CR[10] Y1[10] CB[11] Y0[11] CR[11] Y1[11 ...
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... NXP Semiconductors 13.2 Example of supported video The TDA9981B supports all EIA/CEA-861B, ATSC video input formats. Table 25. Timing parameters for EIA/CEA-861B Format nr. Format 59.94 Hz systems 1 (VGA) 640 480p 2, 3 720 480p 4 1280 720p 5 1920 1080i 6, 7 (NTSC) 720 480i 8, 9 720 240p 8, 9 720 ...
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... Various systems 32 1920 1080p 32 1920 1080p 33 1920 1080p 34 1920 1080p 34 1920 1080p [1] Only for TDA9981BHL/15. Table 26. Timing parameters for PC standards below 150 MHz Standard Format 640 350p 640 400p 720 400p 0.31M3 640 480p VGA 640 480p 640 480p ...
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... Only for TDA9981BHL/15. TDA9981B_1 Product data sheet …continued V frequency H total V total (Hz) 119.989 1184 813 75.000 1600 900 59.995 1440 790 119.798 1440 813 59.870 1664 798 74 ...
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... Cb0 Cb1 Cb2 Cr0 Cr1 Cr2 t h(D) t su( clk(H) clk(L) Cb0 Y0 Cr0 t h( su(D) su(D) Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter B3 ... Bxxx Bxxx G3 ... Gxxx Gxxx R3 ... Rxxx Rxxx Cb3 ... Cbxxx Cbxxx Y3 ... Yxxx Yxxx Cr3 ... Crxxx Crxxx Y1 ... ...
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... Product data sheet t t clk(H) clk(L) Cb0 Y0 Cr0 t h(D) t su( clk(H) clk(L) h( Cb0 Cr0 Cb2 t su(D) Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Y1 ... Crxxx Yxxx Cr2 Cb4 Cr4 © NXP B.V. 2008. All rights reserved. 001aai427 ... ... 001aai428 ...
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... S/PDIF DAC DENC DSP DAC DAC audio AUX 2 I S-bus data or S/PDIF HDMI TX STEREO AUDIO DAC Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter DAC CVBS/Y/(G) DENC DAC C/Pb/(B) DAC Pr/(R) HDMI 8 HDMI TX data stream STEREO AUDIO DAC 001aai429 CVBS/Y/(G) ...
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... TDA9981B 2 S-bus IRQ C-bus I C-bus SLAVE MASTER Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter TMDS clock TMDS channel 0 TMDS channel 1 HDMI RECEIVER/ TMDS channel 2 REPEATER hot plug detect DDC (SCL and SDA) SLAVE E-EDID SLAVE ADDRESS A0 CEC line © ...
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... scale (1) ( 0.27 0.18 12.1 12.1 14.15 14.15 0.5 0.13 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter detail ( 0.75 1.45 1 0.2 0.15 0.1 0.30 1.05 EUROPEAN PROJECTION SOT315 (1) Z ...
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... Solder bath specifications, including temperature and impurities TDA9981B_1 Product data sheet 150 MHz pixel rate HDMI transmitter Rev. 01 — 4 July 2008 TDA9981B © NXP B.V. 2008. All rights reserved ...
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... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 23. Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Figure 23) than a SnPb process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...
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... Digital Versatile Disc Digital Visual Interface End of Active Video Enhanced Extended Display Identification Data Human Body Model High-Definition Multimedia Interface Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter peak temperature time 001aac844 © NXP B.V. 2008. All rights reserved. ...
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... Extended Graphics Array color space used by the NTSC and PAL systems color space originally defined by the ITU-R BT.601 Data sheet status Product data sheet Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter Change notice Supersedes - - © NXP B.V. 2008. All rights reserved. ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 4 July 2008 TDA9981B 150 MHz pixel rate HDMI transmitter © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: TDA9981B_1 All rights reserved. Date of release: 4 July 2008 ...