TSS461 ATMEL Corporation, TSS461 Datasheet
TSS461
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TSS461 Summary of contents
Page 1
... TSS461E, and to use the free RAM as a scratch pad. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link maximum bit rate of 1 Mbit/s. The TSS461E analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks ...
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... Figure 1. Block Diagram AD[7:0] ALE Address and Data Bus Multiplexing logic 128 bytes Message buffer RAM TSS461E 2 INT Status and control bus control data bus registers address bus Protocol controller state machine and ID registers Reception logic CRC generator Data serializer and deserializer ...
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... Multiplexed address and data bus. The address is AD1 22 latched on the falling address of ALE. AD2 23 AD3 24 AD4 1 AD5 2 AD6 3 AD7 4 Address Latch Enable ALE 7 Read Command RD (VSS) 13 Write Command WR (R/W) 14 Chip Select (active high) CS(E) 8 Interrupt INT 6 Asynchronous general reset glitch filtered RESET 19 (12 ns) TSS461E 3 ...
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... TSS461E 4 I/O Type I CMOS Pull-down 3-state Ground Power Ground Pin Name Pin Number Pin Function RXD0 17 VAN bus Inputs RXD1 15 RXD2 16 VAN bus Output TXD 18 Crystal oscillator or clock XTAL1 9 input pins XTAL2 10 Buffered clockout output CKOUT 12 enabled if no reset Oscillator Ground ...
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... Operation The TSS461E is a microprocessor-controlled line controller for the VAN bus. It can interface to virtually any microprocessor, but the I/O signals of the circuit have been optimized for use with the TSC51/TSC251 series of microcontrollers. It features a multiplexed address and data bus, controlled by an address strobe pin ALE and separated read RD and write WR command pins ...
Page 6
... WR active. If TSS461E is the single peripheral in the processor space, CS can be wired to VCC. In Motorola environment, the RD pin is wired to VSS and the access operations are driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to Vcc even if the TSS461E is alone. To switch on-the-fly from one mode to the other, CS must be inactive. Intel Mode The Intel mode interface consists of 13 pins ...
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... WR), but in Motorola mode the reference is the E signal. Figure 4. Motorola Read and Write Cycles Interrupts If an event occurs in the TSS461E, that needs the attention of the processor, this will be sig- nalled on the active low, open-drain interrupt request pin. The events that create this request is controlled by the internal registers. ...
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... Then it waits for eight clock periods the oscillator stability. The different blocks of the TSS461E need to be turned on synchronously. So the release of the internal reset is synchronous and a loose of clock can let the TSS461E in permanent reset after applying Reset ...
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... Oscillator An oscillator is integrated in the TSS461E, and consists of an inverting amplifier which the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As shown in Figure 2, two capacitors have to be connected from the crystal pins to ground. The val- ues of C1 depend on the frequency chosen and can be selected using the graphic given in Figure 34 ...
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... TSS461E 10 8 MHz 6 MHz Kbits/s KTS/s Kbits/s 400 375 300 200 187.50 150 100 93. 46.875+ 37.5 25 23.438 18.75 12.5 11.718 9.375 6.25 5.859 4.688 3 ...
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... VAN Protocol Line Interface There are three line inputs and one line output available on the TSS461E. Each of the three inputs to use is either programmed by software or automatically selected by a diagnosis system. The diagnosis system continuously monitors the data received through the three inputs, and compares them and the selected bitrate ...
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... The Slave module, which can only transmit using an in-frame mechanism and can receive messages. Figure 8. Hierarchical Access Methods Autonomous SOF Rank 0 Rank 1 Rank 16 TSS461E 12 VAN BUS SEQUENCE NORMAL OR PULSED RECESSIVE STATE VAN BUS SEQUENCE NORMAL DOMINANT STATE VAN BUS ...
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... Inter Frame Spacing (IFS) period, to determine whether the bus is free or not (i.e.,no dominant states received). Figure 10. Data Encoding The IFS is defined minimum of 64 prescaled clocks periods. The TSS461E, accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence. 4194C–AUTO–01/06 ...
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... VAN bus are calculated from the current status of the active message. After the command field comes the data field. This is just a sequence of bytes transmitted, MSB first. In the VAN standard the maximum message length is set to 28 bytes, but the TSS461E handles messages bytes. ...
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... However, since the CRC is calculated automatically from the identifier, command and data fields by the TSS461E, the user should not be concerned with the circuit. When the frame check sequence has been transmitted, the transmitting module must transmit an End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to terminate the transfer ...
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... ACK Without acknowlegment TRANSMITTING module RECEIVING module FRAME on bus EXT RAK R/W RTR ACK TSS461E 16 SOF IDENTIFIER SOF IDENTIFIER : Recessive from T ransmitter : Recessive for acknowledge from T ransmitter : Dominant from T ransmitter : Dominant from T ransmitter (*) Manchester bit : Positive from Receiver because RAK is Recessive SOF ...
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... SOF IDENTIFIER : Recessive from Requestor : Recessive for acknowledge from Requestor : Recessive from Requestor : Recessive from Requestor - (*) Manchester bit : Absent from Requestor and Positive from Requestee because RAK is Recessive DATA CRC DATA CRC (*) Manchester bit CRC EOF CRC EOF TSS461E EOF EOF 17 ...
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... EXT : Recessive from Replyer RAK : Recessive for acknowledge from Replyer R/W : Recessive from Replyer RTR : Dominant from Replyer ACK : Absent from Replyer and Positive from Receiver because RAK is Recessive TSS461E 18 IDENTIFIER DATA IDENTIFIER DATA (*) Manchester bit CRC EOF CRC EOF 4194C–AUTO–01/06 ...
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... This is encoded over three bits: Sa, Sb and Sc. Sa and Sb bits indicate the four possible states of the VAN bus. 4194C–AUTO–01/06 The line receiver sensing DATA is connected to RxD1 The line receiver sensing DATA is connected to RxD2 NONIMAL MAJOR ERROR TSS461E DEGRATED DATA 19 ...
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... SDC period. If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode. • Transmission diagnosis: The transmission compares RxD1 and RxD2 inputs (through the input comparators and the TSS461E ...
Page 21
... The TIP turns off synchronously at the end of the transmission: • after EOF • after a losing of arbitration or a code violation detection • for a requester of in frame reply, when the arbitration is lost on RTR the bit. This signal is not generated when the transmission logic only sends an ACK. 4194C–AUTO–01/06 TSS461E 21 ...
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... Programming Four programming modes determine the way for using three different inputs and the diagnosis Modes system. • 3 specified selection modes • 1 automatic selection mode Table 4. Programming Modes TSS461E Operating Mode 0 0 Differential communication 0 1 Degraded communication on RxD2 (DATA Degraded communication on RxD1 (DATA) ...
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... Registers The TSS461E memory map consists of three different areas, the Control & Status registers, the Channel Registers and the Message Data (or Mailbox). Mapping Figure 17. Memory Map 0x78 to 0x7F (r/w) 0x70 to 0x77 (r/w) 0x68 to 0x6F (r/w) 0x60 to 0x67 (r/w) 0x58 to 0x5F (r/w) 0x50 to 0x57 (r/w) 0x48 to 0x4F (r/w) 0x40 to 0x47 (r/w) ...
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... RXD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (default at reset). The TSS461E will set TXD to recessive state in Idle mode and consider the bus free (recessive states on RXD inputs). Transmit Control Register (0x01) • ...
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... The three different module types are supported (see section “VAN Frame”): One: The TSS461E is an autonomous module (Rank 0), an synchronous access module (Rank slave module (Rank 16). Zero: The TSS461E is an synchronous access module (Rank slave module (Rank 16). 4194C–AUTO–01/06 MR [3:0] ...
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... In its two medium order bits the diagnosis system mode is controlled: M1, M0 • In the two low order bits, the user controls if the SDC and TIP are to be generated automatically ETIP, ESDC SDC [3:0]: SDC divider The input clock is the times lot clock. Table 6. System Diagnosis Clock Divider TSS461E SDC2 SDC1 ...
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... One: Sleep active Zero: Sleep inactive 4194C–AUTO–01/ GRES SLEEP IDLE Forces the Communication on RxD0 (differential) Forces the Communication on RxD2 (DATA) Forces the Communication on RxD1 (DATA) Automatic selection ACTI REAR 0 TSS461E MSDC 27 ...
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... IDLE: Idle Command If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will oper- ate, but the TSS461E will not transmit or receive anything on the bus, and the TXD output will be in three-state One: Idle active ...
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... The only way to reset this status bit is through the RI signal or a general reset. TXG: Transmitting If this status bit is active, it indicates that the TSS461E has chosen an identifier to transmit, and it will continue to make transmission attempts for this message until it succeeds or the retry count is exceeded. ...
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... FCSE indicates a mismatch between the FCS received and the FCS calculated Sequence Error One: FCSE active Zero: FCSE inactive ACKE: Acknowledge ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463 is Error produced. One: ACKE active Zero: ACKE inactive TSS461E BOC BOV 3 ...
Page 31
... Zero: CV inactive 4194C–AUTO–01/06 DLC: Producer EOD field ACK field expected RAK = 0 received received received RAK *RAK: bit of the frame COMMAND field EOD field ACK field expected received received received TSS461E ACKE = 0 ACKE = 1 ACKE = 1 ACKE = 1 ACKE = 0 ACKE = 1 ACKE = 1 ACKE = 1 31 ...
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... GRES. This interrupt cannot be disabled, since its enable bit is set when a reset is detected. TE: Transmit Error This flag is set only when the Max number of transmission (1+MR [3:0]) is reached with error of Status Flag (or transmission. Exceeded Retry) Figure 20. Exceeded retry with MR[3. 1st TX TSS461E 32 DLC: Consumer EOD field ACK field ...
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... Reserved bit: 5 and 6. This bit cannot be set by user; a zero must always be written to this bit. 4194C–AUTO–01/ reset the Reset Interrupt Enable bit is set to 1 instead the general rule RSTR TEE TOKE REE ROKE TER TOKR RER ROKR TSS461E 1 0 RNOKE 1 0 RNOKR 33 ...
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... DMA pointers and message status. The base_address of each set is: (0x10 + [0x08 * channel_number]). When the TSS461E is reset either via the external reset pin or the general reset command, the channel registers are not affected. For example, on power-up of the circuit, all the channel regis- ters start with random values ...
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... M_L [4:0] CHER M_P [6:0] ID_T [3: 0] EXT RAK ID_T [11: EXT RAK RNW RTR ID_T 7 ID_T 6 ID_T 5 ID_T 4 TSS461E From To 0x78 0x7F 0x70 0x77 0x68 0x6F 0x60 0x67 0x58 0x5F 0x50 0x57 0x48 0x4F Bit 1 Bit ...
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... In any case link is intended, the three high bits of M_P [6:0] should be set to 0. This allows several channels to use the same actual reception buffer in Message DATA RAM, thus diminishing the memory usage. Note that only 1 level of link is supported. TSS461E ...
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... If the value of this field is "illegal" (i.e 0x00) then this message pointer is defined as being a link (see section “Message Pointer Register” and section “Linked Channels”). CHER: Channel Error As status, this bit is set by the TSS461E when error occurs in transmission received Status and Abort frame. The user must reset it. ...
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... Enable Command channel (seesection “Messages Types”). As a general rule (see section “Abort”), the status bits are only set by the TSS461E, so the user must reset them to perform a transmission or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded ...
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... CHER CHTx CHRx M_L [4..0] SOF ID [11..0] Note: Received DATA Frame, immediate or deffered reply 4194C–AUTO–01/06 Message received DATA n received DATA 0 RAK RNW RTR M_L [4..0] = n+1 received received received received DATA 0 Message Pointer Register M_P [6..0] DRAK M_P + 0x80 + M_P + 0x80 FCS DATA n TSS461E EOF 39 ...
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... This bit is the RTR bit coming from the COM field of the received frame. Bit RM_L[4:0]: Message If the DATA field of the received frame included DATA0 to DATAn, RM_L[4:0] = n+1, even if the Length of the Received reserved length (Message Length & Status Register) is larger. Frame TSS461E 40 Message M_P + 0x80 + DATA n Transmitted ...
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... If the length reserved (in the message length & status register) for an incoming frame is 2 bytes greater or more, the TSS461E will write the 2 bytes of the CRC field in the message string just after DATAn. Because the VAN frame does not contain a message length, the only way for the component to know the length of the DATA field is either the message length register value, or the EOD field detection ...
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... The Reply Request Message type is a demand to transmit on the VAN bus a reply request. When this message type is programmed, three things can happen. First, no other modules on the bus responded with an in-frame reply, in this case the TSS461E will set the message type to the after transmission state. When this message type is pro- grammed, the TSS461E will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request ...
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... Second, another module on the bus replies with an in-frame reply. In this case the message type will pass immediately into the after reception state, without passing the after transmission state. Third, the TSS461E has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warning! This should be avoided as it may result in an illegal message type (Illegal reply Request) ...
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... Priority Among The priority handling on the VAN bus is already explained in the Line Interface section. The pri- orities for the messages in the TSS461E is, however, slightly different. the Different For instance, it's possible that an identifier matches two or more of the identifiers programmed Channels into the registers. In this case the lowest identifier number that has priority. i.e., if both iden- tifier 5 and 10 match the identifier received the identifier 5 that will receive the message ...
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... Register, respectively. An abort command is located in each channel register set, in the Rearbitrate and Message Length & Status Register (base_address + 0x03). These three commands are avail- Abort able only when the TSS461E is producer. Figure 25. Transmit Function Retries The purpose of retries feature is to provide, the capability of retrying a transmit request in case of failure, when a node tries to reach another node, either on normal DATA frame or on REPLY REQUEST frame ...
Page 46
... the retry loop and the user wants to transmit the Ch 5 without waiting the end of the loop, the user can use the rearbitrate command. • Then, the TSS461E will wait the end of the current transmission, reload the retries counter and enable the transmit. • ...
Page 47
... For example, this command can be used to break the retry procedure on one channel. 4194C–AUTO–01/06 Delay Viol EOF+IFS EOF+IFS In this case, the TSS461E completes the current attempt (Ch8) and lets the transmission go to the new channel (Ch5 if validated); otherwise, it stops all attempts on the current channel. TSS461E Idle Delay Delay Viol ...
Page 48
... Abort channel is done by setting the Error bit (CHER) in the Message Length & Status Register (base_address + 0x02). This command is taken into account if the channel aborted is not trans- mitted. When this abort command is really done, the TSS461E set to 1 the Transmitted bit (CHTx) of the Message Length & Status Register. ...
Page 49
... To exit from this mode, the user must set either the idle bit or the activate bit typical application (Figure 12) using the CKOUT feature (pin 12), if the TSS461E is put in sleep mode, the clock provided to the microcontroller is stopped. So, the system does not run and the only way to awake this application is an external reset. 4194C– ...
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... ID_Mask i (lsb) ID_Mask i (msb) Mess_Len = n+2 DRAK ID_Tag i (lsb) ID_Tag i (msb) This Message Area sharing permits either optimizing the allocation of the 128 bytes of DATA, performing some special communications between the different nodes of the network. TSS461E 50 The Channel j linked . . . . to the Channel i CHER CHTx CHRx i ...
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... SS Min Max -0.5 0.8 2.0 V +0.5 CC -0.5 0.3· 0.4 2.4 +5 110 Clock Signal TSS461E Type Test Conditions See Figure 3.2 mA, Vcc min -3.2 mA, Vcc min OH μA 0 < V < kΩ 0 < V < Not tested μA (Note 1) ...
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... Figure 32. I Figure 33. ICC Versus Clock Frequency at 250 KTimeslot/s TSS461E 52 CC CLOCK SIGNAL N. 8.5 8 7.5 2 Icc TXD MHz 4194C–AUTO–01/06 ...
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... Read Active to Data Valid Access Time RLDV 9 T Read Inactive to Data Float Time RHDZ 10 T Write Inactive or Read Active to IRQ Float Time WHRLIZ 11 T IRQ Float Pulse Width IZIL 4194C–AUTO–01/ TSS461E Min Max Unit ...
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... Oscillator Figure 34. C2 Versus Frequency Characteristics Note: External Clock Drive Characteristics (XTAL1) TSS461E 54 pF 200 100 (no capacitance needed) see Figure 2. Symbol Parameter T Oscillator Period CHCH T High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL XTAL1 ...
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... Packaging Information 4194C–AUTO–01/ 2.35 A1 0.10 B 0.35 C 0.23 D 15.20 E 7.40 e 1.27 H 10.00 h 0. 0° INCH 2.65 0.093 0.30 0.004 0.49 0.014 0.32 0.009 15.60 0.599 7.60 0.291 BSC 0.050 10.65 0.394 0.75 0.010 1.27 0.016 24 0° TSS461E 0.104 0.012 0.019 0.013 0.614 0.299 BSC 0.419 0.029 0.050 55 ...
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... Ordering Information Part Number Supply Voltage TSS461E-TDSA-9 TSS461E-TDRA-9 (1) TSS461E-TDRZ-9 Note: 1. These products are available in ROHS version. TSS461E 56 Temperature Range 5V +10% -40°C to +125°C 5V +10% -40°C to +125°C 5V +10% -40°C to +125°C Package Packing SO24 Tube SO24 Tape & Reel SO24 Tape & Reel ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’sAtmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...