w83697 Winbond Electronics Corp America, w83697 Datasheet
w83697
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w83697 Summary of contents
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... W83697HF/F WINBOND I/O ...
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... Winbond for any damages resulting from such improper use or sales. Version Version on Web First published. 0.40 For Beta Site customers only 0.41 H/W monitor register correction 0.50 New composition Add W83697F pin assignment & Notice 0.6 0.7 New Update Main Contents ...
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... FRESH ROM INTERFACE .............................................................................................................................................. 14 1.7 HARDWARE MONITOR INTERFACE ........................................................................................................................ 15 1.8 GAME PORT & MIDI PORT........................................................................................................................................... 16 1.9 POWER PINS..................................................................................................................................................................... 17 2. LPC (LOW PIN COUNT) INTERFACE.....................................................................18 3. FDC FUNCTIONAL DESCRIPTION........................................................................19 3.1 W83697HF FDC................................................................................................................................................................. 19 3.1.1 AT interface...............................................................................................................................................................19 3.1.2 FIFO (Data)..............................................................................................................................................................19 3.1.3 Data Separator.........................................................................................................................................................20 3.1.4 Write Precompensation...........................................................................................................................................20 3.1.5 FDC Core ..................................................................................................................................................................21 3.1.6 FDC Commands .......................................................................................................................................................21 3.1.7 FDC Commands .......................................................................................................................................................21 3.2 REGISTER DESCRIPTIONS ............................................................................................................................................ 34 3 ...
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... Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) .....................................................................................61 5.1.10 Bank1.Reg2 - Version ID Regiister I (VID) ....................................................................................................... 62 5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .....................62 5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL)..............................................................................................62 5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ............................................................................................ 62 6. PARALLEL PORT...................................................................................................... 63 6.1 PRINTER INTERFA CE LOGIC........................................................................................................................................ 63 W83697HF/F Publication Release Date: Feb. 2002 - II - Revision 0.70 ...
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... ECP Pin Descriptions...........................................................................................................................................75 6.3.13 ECP Operation.......................................................................................................................................................76 6.3.14 FIFO Operation .....................................................................................................................................................76 6.3.15 DMA Transfers........................................................................................................................................................77 6.3.16 Programmed I/O (NON-DMA) Mode .................................................................................................................77 6.4 EXTENSION FDD MODE (EXTFDD)............................................................................................................................ 77 6.5 EXTENSION 2FDD MODE (EXT2FDD)........................................................................................................................ 77 7. GENERAL PURPOSE I/O...........................................................................................78 8. ACPI REGISTERS FEATURES .................................................................................81 9. HARDWARE MONITOR ..........................................................................................82 9.1 GENERAL DESCRIPTION............................................................................................................................................... 82 9.2 ACCESS INTERFACE...................................................................................................................................................... 82 W83697HF/F Publication Release Date: Feb. 2002 - III - Revision 0.70 ...
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... Fan speed control....................................................................................................................................................89 9.5 SMI# INTERRUPT MODE.............................................................................................................................................. 90 9.5.1 Voltage SMI# mode :...............................................................................................................................................90 9.5.2 Fan SMI# mode :......................................................................................................................................................90 9.5.3 Temperature SMI# mode.........................................................................................................................................91 9.5.4 The W83697HF temperature sensor 2 and sensor 3 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6......................................................................................................................................................92 9.6 OVT# INTERRUPT MODE.............................................................................................................................................. 93 9.7 REGISTERS AND RAM................................................................................................................................................... 94 9.7.1 Address Register (Port x5h)...................................................................................................................................94 9.7.2 Data Register (Port x6h)........................................................................................................................................97 9.7.3 Configuration Register ¾ ...
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... Winbond Test Register -- Index 50h (Bank 6) ............................................................................................... 117 9.7.50 FAN 1 Pre-Scale Register ndex00h............................................................................................................. 117 9.7.51 FAN 1 Duty Cycle Select Register-- 01h (Bank 0)....................................................................................... 118 9.7.52 FAN 2 Pre-Scale Register-- Index 02h............................................................................................................ 118 9.7.53 FAN2 Duty Cycle Select Register-- Index 03h .............................................................................................. 119 9.7.54 FAN Configuration Register-- Index 04h ....................................................................................................... 119 W83697HF/F Publication Release Date: Feb. 2002 - V - Revision 0.70 ...
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... LOGICAL DEVICE 6 (CIR)........................................................................................................................................... 139 10.10 LOGICAL DEVICE 7 (GAME PORT GPIO PORT 1)............................................................................................... 139 10.11 LOGICAL DEVICE 8 (MIDI PORT AND GPIO PORT 5)....................................................................................... 140 10.12 LOGICAL DEVICE 9 (GPIO PORT 2 ~ GPIO PORT 4 ).......................................................................................... 142 10.13 LOGICAL DEVICE A (ACPI)..................................................................................................................................... 144 10.14 LOGICAL DEVICE B (HARDWARE MONITOR).................................................................................................. 148 W83697HF/F Publication Release Date: Feb. 2002 - VI - Revision 0.70 ...
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... ORDERING INSTRUCTION...................................................................................149 12. HOW TO READ THE TOP MARKING..................................................................149 13. PACKAGE DIMENSIONS.......................................................................................150 W83697HF/F Publication Release Date: Feb. 2002 - VII - Revision 0.70 ...
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... The W83697HF is made to fully comply with Microsoft PC98 and PC99 Hardware Design Guide, and meet the requirements of ACPI. The W83697HF contains a game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, They are very important for a entertainment or consumer computer ...
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... The W83697HF provides Flash ROM interface. That can support legacy flash ROM. The W83697HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. ...
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... Support two separate Joysticks Support every Joystick two axes (X,Y) and two buttons (S1,S2) controllers MIDI Port The baud rate is 31.25 Kbaud 16-byte input FIFO 16-byte output FIFO Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification Publication Release Date:Feb. 2002 - 3 - W83697HF 16 -1) Revision 0.70 ...
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... Over temperature indicate output Automatic Power On voltage detection Beep Issue SMI#, IRQ, OVT# to activate system protection Winbond Hardware Doctor TM Intel LDCM / Acer ADM Package 128-pin PQFP TM ” and “Speed Cruise TM Support TM compatible - 4 - W83697HF TM ” TM II/III thermal Publication Release Date:Feb. 2002 Revision 0.70 ...
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... W83697HF IRRX 64 RIB# 63 DCDB# 62 SOUTB 61 GND 60 SINB 59 DTRB# 58 RTSB# 57 DSRB# 56 CTSB# 55 RIA# ...
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... Serial IRQ input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... K resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN). The read data input signal from the FDD. This input pin is pulled up internally resistor. The resistor can be disabled by bit 7 of L0-CRF0 (FIPURDWN W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... ECP and EPP mode. EXTENSION FDD MODE: WD2# This pin is for Extension FDD B; its function is the same as the WD# pin of FDC. EXTENSION 2FDD MODE: WD2# This pin is for Extension FDD A and B; its function is the same as the WD# pin of FDC W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... ECP and EPP mode. EXTENSION FDD MODE: HEAD2# This pin is for Extension FDD B; its function is the same as the HEAD#pin of FDC. EXTENSION 2FDD MODE: HEAD2# This pin is for Extension FDD A and B; its function is the same as the HEAD# pin of FDC W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... EXTENSION FDD MODE: DRVDEN0 This pin is for Extension FDD B; its function is the same as the DRVDEN0 pin of FDC. EXTENSION 2FDD MODE: DRVDEN0 This pin is for Extension FDD A and B; its function is the same as the DRVDEN0 pin of FDC W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... This pin is for Extension FDD B; its function is the same as the WP# pin of FDC pulled high internally. EXTENSION. 2FDD MODE: WP2# This pin is for Extension FDD A and B; its function is the same as the WP# pin of FDC pulled high internally W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... ECP and EPP mode. EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION 2FDD MODE: DSA2# This pin is for Extension FDD A; its function is the same as the DSA# pin of FDC W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... CR24 bit 6 (EN48). A 4.7 k resistor is recommended if intends to pull up. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... Flash ROM interface Data Bus [3:0] General purpose I/O port 2 bit3-0 Flash ROM interface Chip Select General purpose I/O port 5 bit4 Flash ROM interface Memory Read Enable General purpose I/O port 5 bit3 Flash ROM interface Memory Write Enable General purpose I/O port 5 bit2 - 14 - W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... Fan speed control. Use the Pulse Width Modulatuion (PWM) technic knowledge to control the Fan's RPM. Over temperature Shutdown Output. It indicated the VTIN1 or VTIN2 is over temperature limit. System Management Interrupt. Beep function for hardware monitor. This pin is low after system reset W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... General purpose I/O port 1 bit 2. Active-low, Joystick II switch input 1. This pin has an internal pull- up resistor. (Default) General purpose I/O port 1 bit 1. Active-low, Joystick I switch input 1. This pin has an internal pull- up resistor. (Default) General purpose I/O port 1 bit W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... Analog VCC input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground reference for all analog inputs.. Ground W83697HF Publication Release Date:Feb. 2002 Revision 0.70 ...
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... Comparing to its ISA counterpart, LPC implementation saves pin counts free for integrating more devices on a single chip. The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. W83697HF Publication Release Date:Feb. 2002 - 18 - Revision 0.70 ...
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... FDC FUNCTIONAL DESCRIPTION 3.1 W83697HF FDC The floppy disk controller of the W83697HF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate. ...
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... The FDC monitors the bit stream t hat is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits. W83697HF/F Publication Release Date: Feb. 2002 - 20 - Revision 0.70 ...
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... FDC Core The W83697HF FDC is capable of performing twenty commands. Each command is initiated by a multi- byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. ...
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... RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE W83697HF/F Publication Release Date: Feb. 2002 - 22 - Revision 0.70 ...
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... HDS DS1 Publication Release Date: Feb. 2002 - 23 - W83697HF/F D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision 0.70 ...
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... HDS DS1 Publication Release Date: Feb. 2002 - 24 - W83697HF/F D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision 0.70 ...
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... HDS DS1 Publication Release Date: Feb. 2002 - 25 - W83697HF/F D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after ...
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... HDS DS1 Publication Release Date: Feb. 2002 - 26 - W83697HF/F D0 REMARKS 0 Command codes DS0 The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed Revision 0.70 ...
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... R ------------------------ R ---------------------- N ------------------------ HDS DS1 Publication Release Date: Feb. 2002 - 27 - W83697HF/F D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution No data transfer takes place Status information after command execution Sector ID information after command execution Revision 0.70 ...
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... HDS DS1 Publication Release Date: Feb. 2002 - 28 - W83697HF/F D0 REMARKS 0 Command code 0 Enhanced controller D0 REMARKS 1 Command codes DS0 Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution ...
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... HDS DS1 Publication Release Date: Feb. 2002 - 29 - W83697HF/F D0 REMARKS 1 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision 0.70 ...
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... HDS DS1 DS1 Publication Release Date: Feb. 2002 - 30 - W83697HF/F D0 REMARKS 1 Command codes DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D0 REMARKS 1 Command codes DS0 Head retracted to Track 0 Interrupt ...
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... HDS DS1 EIS EFIFO POLL | ------ FIFOTHR ----| Publication Release Date: Feb. 2002 - 31 - W83697HF/F D0 REMARKS 0 Command code D0 REMARKS 1 Command codes D0 REMARKS 1 Command codes DS0 Head positioned over proper cylinder on diskette D0 REMARKS 1 Configure information 0 Internal registers written ...
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... D1 D0 GAP GAP LOCK Publication Release Date: Feb. 2002 - 32 - W83697HF/F D0 REMARKS 1 Command codes DS0 D0 REMARKS 0 Registers placed in FIFO WG D0 REMARKS 0 Command Code WG D0 REMARKS Command Code 0 0 Revision 0.70 ...
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... Invalid Codes ----------------- Result HDS DS1 -------------------- ST0 ---------------------- Publication Release Date: Feb. 2002 - 33 - W83697HF/F D0 REMARKS Command Code 0 DS0 Status information about disk drive D0 REMARKS Invalid codes (no operation- FDC goes to standby state) ST0 = 80H Revision 0.70 ...
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... Register Descriptions There are several status, data, and control registers in W83697HF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 3.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, ...
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... This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched STEP# output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0# input. output DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING Publication Release Date: Feb. 2002 - 35 - W83697HF/F Revision 0.70 ...
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... This bit changes state at every rising edge of the RDATA# output pin. WE (Bit 2): This bit indicates the complement of the WE# output pin. output MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 Publication Release Date: Feb. 2002 - 36 - W83697HF/F Revision 0.70 ...
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... This bit indicates the complement of latched WE# output pin. DSD# (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC# (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 Publication Release Date: Feb. 2002 - 37 - W83697HF/F Revision 0.70 ...
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... Motor Enable D. Motor D on when active high Tape sel 0 Tape sel Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 Publication Release Date: Feb. 2002 - 38 - W83697HF/F Revision 0.70 ...
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... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. Publication Release Date: Feb. 2002 - 39 - W83697HF Revision 0.70 ...
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... DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 0.00 nS (disabled) Publication Release Date: Feb. 2002 - 40 - W83697HF/F 2 Mbps Tape drive Default Delays 20.8 nS 41.17 nS 62.5nS 83.3 nS 104.2 nS 125.00 nS 0.00 nS (disabled) Revision 0.70 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83697HF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder. Publication Release Date: Feb. 2002 - 42 - W83697HF/F Revision 0.70 ...
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... CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Publication Release Date: Feb. 2002 - 43 - W83697HF/F Revision 0.70 ...
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... Reserved for the hard disk controller During a read of this register, these bits are in tri-state DSKCHG HIGH DENS DRATE0 DRATE1 DSKCHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG Publication Release Date: Feb. 2002 - 44 - W83697HF/F Revision 0.70 ...
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... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved DRATE0 DRATE1 NOPREC : X Reserved Publication Release Date: Feb. 2002 - 45 - W83697HF/F DRATE0 DRATE1 Revision 0.70 ...
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... Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB) Publication Release Date: Feb. 2002 - 46 - W83697HF/F Revision 0.70 ...
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... CTS DSR RI Falling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83697HF Data RX Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Publication Release Date: Feb. 2002 - 48 - W83697HF/F Revision 0.70 ...
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... FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset gical 0. W83697HF/F Publication Release Date: Feb. 2002 - 49 - ...
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... Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS , Loopback RI input ( bit 2 of HCR) DCD . Publication Release Date: Feb. 2002 - 50 - W83697HF/F Revision 0.70 ...
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... Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Publication Release Date: Feb. 2002 - 51 - W83697HF/F Revision 0.70 ...
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... Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB Publication Release Date: Feb. 2002 - 52 - W83697HF/F Revision 0.70 ...
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... TBR Empty TBR empty Handshake status 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 Publication Release Date: Feb. 2002 - 53 - W83697HF/F Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2. Read ISR (if priority is ...
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... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) Publication Release Date: Feb. 2002 - 54 - W83697HF/F 16 -1. The output frequency of Revision 0.70 ...
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... Hz 650 2304 975 1536 1430 1047 1478.5 857 1950 768 3900 384 7800 192 15600 96 23400 64 26000 58 31200 48 46800 32 62400 24 93600 16 124800 12 249600 6 499200 3 748800 2 1497600 1 Publication Release Date: Feb. 2002 - 55 - W83697HF/F Error Percentage between desired and actual ** ** 0.18% 0.099 0.53 Revision 0.70 ...
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... Receiver Buffer Register (RBR) is equal or larger than the threshold level, (2) RBR occurs time-out if the receiver buffer register has valid data and below the threshold level. Clear to 0 when RBR is less than threshold level from reading RBR. Publication Release Date: Feb. 2002 - 56 - W83697HF/F (2) EN_TMR(Enable Revision 0.70 ...
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... Enable timer. Write to 1, enable the t imer Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a logical 0 by itself after being set to a logical 1. Timer input clock. Winbond test register Publication Release Date: Feb. 2002 - 57 - W83697HF/F Revision 0.70 ...
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... Receiver Frequency Select 4~0. Select the receiver operation frequency. RX_FR2~0 (Low Frequency) 010 Max. Min. Max. 29.6 24.7 31.7 32.0 26.7 34.3 33.3 27.8 35.7 34.0 28.4 36.5 35.6 29.6 38.1 36.4 30.3 39.0 37.2 31.0 39.8 38.1* 31.7 40.8 39.0 32.5 41.8 41.0 34.2 44.0 42.1 35.1 45.1 43.2 36.0 46.3 45.7 38.1 49.0 47.1 39.2 50.4 48.5 40.4 51.9 50.0 41.7 53.6 51.6 43.0 55.3 55.2 46.0 59.1 57.1 47.6 61.2 61.5 51.3 65 W83697HF/F 011 Min. Max. 23.4 34.2 25.3 36.9 26.3 38.4 26.9 39.3 28.1 41.0 28.7 42.0 29.4 42.9 30.1 44.0 30.8 45.0 32.4 47.3 33.2 48.6 34.1 49.9 36.1 52.7 37.2 54.3 38.3 56.0 39.5 57.7 40.7 59.6 43.6 63.7 45.1 65.9 48.6 71.0 Publication Release Date: Feb. 2002 Revision 0.70 ...
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... Bit value The Bit value is set to 0, then the high pulse will be received. The Bit value is set to 1, then no energy will be received. The opposite results will be generated when the bit RXINV (Bank0.Reg6.Bit0) is set to 1. Publication Release Date: Feb. 2002 - 59 - W83697HF/F Revision 0.70 ...
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... Cleared Upon Read. - FIFO Level Value. Indicate that how many bytes are there in the current received FIFO. Can read these bits then get the FIFO level value and successively read RBR by the prior value. Publication Release Date: Feb. 2002 - 60 - W83697HF/F Revision 0.70 ...
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... The percentage error for all baud rates, except where indicated otherwise, is 0.16% Decimal divisor used to Percent error difference between generate 16X clock 2304 1536 1047 857 768 384 192 Note 1 1 Publication Release Date: Feb. 2002 - 61 - W83697HF/F desired and actual ** ** 0.18% 0.099 0.53 Revision 0.70 ...
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... EN_TMR=1, the TMR_I is set to 1. When the counter down count to zero, a new initial value will be re-loaded into timer counter. Description Reserved. Timer High Byte Register. See Bank1.Reg4. Publication Release Date: Feb. 2002 - 62 - W83697HF ms. The timer Revision 0.70 ...
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... Intr I BUSY nWait SLCT Select O nAFD nDStrb I nERR nError O nINIT nInit O nSLIN nAStrb Publication Release Date: Feb. 2002 - 63 - W83697HF/F ECP 2 nSTB, HostClk PD<0:7> 2 nACK, PeriphClk 2 BUSY, PeriphAck 2 PEerror, nAckReverse 2 SLCT, Xflag 2 nAFD, HostAck 1 2 nFault , nPeriphRequest 1 2 nINIT , nReverseRqst 1 2 ...
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... OD REGISTER Data port (R/W) Printer status buffer (Read) Printer control latch (Write) Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/ W83697HF/F EXT2FDD PIN EXTFDD ATTRIBUTE --- --- --- INDEX2# I INDEX2# TRAK02# I TRAK02# ...
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... Writing a logic 1 to this bit will clear the time-out status bit; writing a logic 0 has no effect TMOUT ERROR SLCT PE ACK BUSY ACK# BUSY# stops. S time-out has occurred on the EPP - 65 - W83697HF/F signal means the printer has Publication Release Date: Feb. 2002 Revision 0.70 ...
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... The address port is available only in EPP mode. Bit definitions are as follows STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR ACK# changes from low to high W83697HF/F PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date: Feb. 2002 Revision 0.70 ...
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... PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 - 67 - W83697HF/F IOR# causes an EPP read PD2 PD1 PD0 1 1 TMOUT INIT# AUTOFD# STROBE# INIT# AUTOFD# STROBE# PD2 PD1 PD0 PD2 ...
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... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high. W83697HF/F EPP DESCRIPTION Publication Release Date: Feb. 2002 - 68 - ...
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... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: Feb. 2002 - 69 - W83697HF/F FUNCTION Revision 0.70 ...
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... W83697HF/F Publication Release Date: Feb. 2002 - 70 - Revision 0.70 ...
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... These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE nFault Select PError nAck nBusy - 71 - W83697HF/F Publication Release Date: Feb. 2002 Revision 0.70 ...
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... Bit 2: This bit is output to the INIT# output. Bit 1: This bit is inverted and output to the AFD# output. Bit 0: This bit is inverted and output to the STB# output strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date: Feb. 2002 - 72 - W83697HF/F Revision 0.70 ...
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... Bit 7: This bit is read -only low level during a read. This means that this chip does not support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts IRQx 0 IRQx 1 IRQx 2 intrValue compress - 73 - W83697HF/F Publication Release Date: Feb. 2002 Revision 0.70 ...
Page 83
... Test Mode. The FIFO may be written and read in this mode, but the data will not be transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and 0x401 in this mode. IRQ resource empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date: Feb. 2002 - 74 - W83697HF/F . Revision 0.70 ...
Page 84
... PD5 PD4 PD3 PD2 PError Select nFault Directio ackIntEn SelectIn nInit nErrIntrEn dmaEn serviceIntr Publication Release Date: Feb. 2002 - 75 - W83697HF NOTE PD1 PD0 autofd strobe full empty Revision 0.70 ...
Page 85
... ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. Publication Release Date: Feb. 2002 - 76 - W83697HF/F Revision 0.70 ...
Page 86
... The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. W83697HF/F Publication Release Date: Feb. 2002 - 77 - Revision 0.70 ...
Page 87
... Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output. (4) If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive. W83697HF/F Publication Release Date: Feb. 2002 - 78 - Revision 0.70 ...
Page 88
... GENERAL PURPOSE I/O W83697HF provides 24 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 24 GP I/O ports are divided into three groups, each group contains 8 port s. The first group is configured through control registers in logical device 7, the second group in logical device 8, and the third group in logical device 9. Users can configure each individual port input or output port by programming respective bit in selection register (CRF0 output input) ...
Page 89
... BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 BIT 6 GP26 BIT 7 GP27 BIT 0 GP30 BIT 1 GP31 BIT 2 GP32 BIT 3 GP33 BIT 4 GP34 BIT 5 GP35 BIT 6 GP36 BIT 7 GP37 Publication Release Date: Feb. 2002 - 80 - W83697HF/F Revision 0.70 ...
Page 90
... W83697HF/F Figure 7.1 Publication Release Date: Feb. 2002 - 81 - Revision 0.70 ...
Page 91
... ACPI REGISTERS FEATURES W83697HF supports both ACPI and legacy power managements. management block generates an SMI interrupt in the legacy mode and an PME interrupt in the ACPI mode. The new ACPI feature routes SMI / PME SMI / logic routes to SMI only when both PME_EN = 0 and SMIPME_OE = 1. Similarly, the SMI / PME logic routes to PME only when both PME_EN = 1 and SMIPME_OE = 1 ...
Page 92
... The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports is set by W83697HF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port ...
Page 93
... ISA Data Address Bus Bus Port 5h Index Register Port 6h Data Register Figure 9.1 : ISA interface access diagram - 84 - W83697HF/F Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h Fan Divisor Register 47h Device ID 48h Monitor Value Registers 20h~3Fh and 60h~7Fh (auto -increment) VID< ...
Page 94
... ADC. The Pin 97 is connected to the power supply VCC with +5V. There are two functions in this pin with 5V. The first function is to supply internal analog power in the W83697HF and the second function is that this voltage with 5V is connected to internal serial resistors to monitor the +5V voltage ...
Page 95
... V in The Pin 61 is connected to 5VSB voltage. W83697HF monitors this voltage and the internal two serial resistors are 17K and 33K so that input voltage to ADC is 3.3V which less than 4.096V of ADC maximum input voltage. 9.3.2 Monitor negative voltage: The negative voltage should be connected two series resistors and a positive voltage VREF (is equal to 3 ...
Page 96
... The W83697HF can alternate the thermistor to Pentium II transistor 2N3904 and the circuit connection is shown as Figure 9.3. The pin of Pentium II connected to power supply ground (GND) and the pin D+ is connected to pin VTINx in the W83697HF. The resistor R=30K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise ...
Page 97
... That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, PRM, and count. VREF R=30K, 1% VTINx C=3300pF W83697HF R=30K VTINx C=3300pF D- Figure 9 Count RPM Divisor Publication Release Date: Feb. 2002 - 88 - W83697HF/F Revision 0.70 ...
Page 98
... Figure 9.4 Publication Release Date: Feb. 2002 - 89 - W83697HF/F 70% RPM Time for 70% 6160 9.74 ms 3080 19.48 ms 1540 38.96 ms 770 77.92 ms 385 155.84 ms 192 311. 623. 1246.72 ms Pull-up resister 4.7K Ohms 14K~39K Fan Input 10K W83697HF Pull-up resister < totem-pole output Fan Input > 1K 3.9V Zener W83697HF Revision 0.70 ...
Page 99
... Fan speed control The W83697HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows ...
Page 100
... Status Register. (Figure 9.7 ) High limit Low limit SMI# * *Interrupt Reset when Interrupt Status Registers are read Figure 9.6 Fan Count limit SMI Publication Release Date: Feb. 2002 - 91 - W83697HF Figure 9.7 Revision 0.70 ...
Page 101
... The W83697HF temperature sensor 1 SMI# interrupt has two modes: (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127 ° C will set temperature sensor 1 SMI# to the HYST Comparator Interrupt Mode. Temperature exceeds T and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event ...
Page 102
... The W83697HF temperature sensor 2 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode: Temperature exceeding T causes an interrupt and this interrupt will be reset by reading all the O Interrupt Status Register. Once an interrupt event has occurred by exceeding T temperature remains above the T completed ...
Page 103
... OVT# interrupt mode The OVT# signal is only related with temperature sensor 2. 9.6.1 The W83697HF temperature sensor 2 Over-Temperature (OVT#) has the following modes (1) Comparator Mode(Default): Setting Bank1/2 CR[52h] bit will set OVT# signal to comparator mode. Temperature exceeding T causes the OVT# output activated until the temperature is less than ...
Page 104
... To T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) *Interrupt Reset when Temperature 2/3 is read OVT# pin signal in ACPI mode ('C) 100 OVT# W83697HF Current Temperature Publication Release Date: Feb. 2002 - 95 - Revision 0.70 ...
Page 105
... Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With checking this bit, multiple LPC drivers can use W83697HF hardware monitor without interfering with each other or a Serial Bus driver the user's responsibility not to have a Serial Bus and LPC bus operations at the same time. ...
Page 106
... SMIÝ Mask Register 2 after a read or write to Port x6h. 00000000 00000000 Auto-increment to the address of NMI Mask Register 2 after a read or write to Port x6h 01000000 <7:4> = 0101; <7:1> = 0000001 <7:0> = 00000000 <7:0> = 00010101 <7> <6:3> = Reserved ; <2:0> = 000 <7:0> = 01011100 (High Byte) <7:0> = 10100011 (Low Byte) Publication Release Date: Feb. 2002 - 97 - W83697HF/F Notes Revision 0.70 ...
Page 107
... Additional Configuration Bank4 Registers 50h-5Dh Power On Value of Registers: <k7:0>in Binary Auto-increment to the next location after a read or write to Port x6h and stop at 1Fh. Auto-increment to the next location after a read or write to Port x6h and stop at 7Fh. Publication Release Date: Feb. 2002 - 98 - W83697HF/F Notes Revision 0.70 ...
Page 108
... Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit Data Index 40h START SMI#Enable RESERVED INT_Clear RESERVED RESERVED RESERVED INITIALIZATION Publication Release Date: Feb. 2002 - 99 - W83697HF/F Revision 0.70 ...
Page 109
... W83697HF/F Publication Release Date: Feb. 2002 - 100 - Revision 0.70 ...
Page 110
... Attribute: Read Only Size: 8 bits 7 6 Index 41h VCORE Reserved +3.3VIN AVCC TEMP1 TEMP2 FAN1 FAN2 Index 42h +12VIN -12VIN -5VIN Reserved CaseOpen Reserved Reserved Reserved Publication Release Date: Feb. 2002 - 101 - W83697HF/F Revision 0.70 ...
Page 111
... Bit 5-0: A one disables the corresponding interrupt status bit for SMI interrupt. Index 43h VCORE Reserved +3.3VIN AVCC TEMP1 TEMP2 FAN1 FAN2 Index 44h +12VIN -12VIN -5VIN Reserved CaseOpen Reserved Reserved Reserved Publication Release Date: Feb. 2002 - 102 - W83697HF/F Revision 0.70 ...
Page 112
... W83697HF/F Publication Release Date: Feb. 2002 - 103 - Revision 0.70 ...
Page 113
... Note : Please refer to Bank0 CR[5Dh] , Fan divisor table Reserved Reserved Reserved Reserved Reserved Reserved Reserved Chassis Clear Index 47h Reserved Reserved Reserved Reserved FAN1DIV_B0 FAN1DIV_B1 FAN2DIV_B0 FAN2DIV_B1 Publication Release Date: Feb. 2002 - 104 - W83697HF/F Revision 0.70 ...
Page 114
... W83697HF/F Description VCORE reading Reserved +3.3VIN reading AVCC(+5V) reading +12VIN reading -12VIN reading -5VIN reading Temperature sensor 1 reading FAN1 reading Note: This location stores the number of counts of the internal clock per revolution. ...
Page 115
... Note the number of counts of the internal clock for the Low Limit of the fan speed. FAN2 Fan Count Limit Note the number of counts of the internal clock for the Low Limit of the fan speed. Reserved. Reserved Reserved DID<6:0> Publication Release Date: Feb. 2002 - 106 - W83697HF/F Revision 0.70 ...
Page 116
... Reserved - Index 4Bh W83697HF/F Publication Release Date: Feb. 2002 - 107 - Revision 0.70 ...
Page 117
... Bit 1: Reserved. Bit 0: Reserved. 9.7.15 FAN IN/OUT and BEEP Control Register- Index 4Dh Register Location: 4Dh Power on Default Value 15h Attribute: Read/Write Size: 8 bits En_ACPI_OVT Reserved OVTPOL DIS_OVT Reserved SMI_INTMode T2_INTMode Reserved Publication Release Date: Feb. 2002 - 108 - W83697HF/F Revision 0.70 ...
Page 118
... Bit 6-3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select FANINC1 FANOPV1 FANINC2 FANOPV2 Reserved Reserved Reserved Reserved BANKSEL0 BANKSEL1 BANKSEL2 Reserved Reserved Reserved Reserved HBACS Publication Release Date: Feb. 2002 - 109 - W83697HF/F Revision 0.70 ...
Page 119
... W83697HF/F Publication Release Date: Feb. 2002 - 110 - Revision 0.70 ...
Page 120
... Bit 6: Enable BEEP Output from FAN 1 if the monitor value exceed the limit value. Write 1, enable BEEP output, which is default value VIDH VIDL EN_VC_BP Reserved EN_V33_BP EN_AVCC_BP EN_T1_BP EN_T2_BP EN_FAN1_BP EN_FAN2_BP Publication Release Date: Feb. 2002 - 111 - W83697HF/F Revision 0.70 ...
Page 121
... Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 W83697HF/F Publication Release Date: Feb. 2002 - 112 - Revision 0.70 ...
Page 122
... Bit 0: Enable BEEP output from +12V, Write 1, enable BEEP output if the monitor value exceed the limits value. Default 0, that is disable BEEP output EN_V12_BP EN_NV12_BP EN_NV5_BP Reserved EN_CASO_BP Reserved Reserved EN_GBP Publication Release Date: Feb. 2002 - 113 - W83697HF/F Revision 0.70 ...
Page 123
... Bit 4: Temperature sensor diode 1. Set to 1, select CPU compatible Diode. Set select 2N3904 Bipolar mode. Bit 3-0: Reserved CHIPID Reserved Reserved Reserved Reserved SELPIIV1 SELPIIV2 Reserved Reserved Publication Release Date: Feb. 2002 - 114 - W83697HF/F Revision 0.70 ...
Page 124
... Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. If enable this bit, the monitor value is value after one monitor cycle. Note that the monitor cycle time is at least 300ms for W83697HF hardware monitor. Fan divisor table : Bit 2 ...
Page 125
... Temperature Sensor 2 Temperature (Low Byte) Register - Index 51h ( Bank 1 ) Register Location: 51h Attribute: Read Only Size: 8 bits 7 6 Bit 7: Temperature <0> of sensor2, which is low byte, means 0.5 C. Bit 6-0: Reserved TEMP2<8:1> Reserved TEMP2<0> Publication Release Date: Feb. 2002 - 116 - W83697HF/F Revision 0.70 ...
Page 126
... Power on Default Value 4Bh Attribute: Read/Write Size: 8 bits 7 6 Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree STOP2 INTMOD Reserved FAULT FAULT Reserved Reserved Reserved THYST2<8:1> Publication Release Date: Feb. 2002 - 117 - W83697HF/F Revision 0.70 ...
Page 127
... Temperature Sensor 2 Over-temperature (High Byte) Register - Index 55h ( Bank 1 ) Register Location: 55h Power on Default Value 50h Attribute: Read/Write Size: 8 bits 7 6 Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree Reserved THYST2<0> TOVF2<8:1> Publication Release Date: Feb. 2002 - 118 - W83697HF/F Revision 0.70 ...
Page 128
... Bit 1: A one indicates Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of 5VSB has been exceeded Reserved TOVF2<0> 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved Publication Release Date: Feb. 2002 - 119 - W83697HF/F Revision 0.70 ...
Page 129
... Bit 0: Enable BEEP Output from 5VSB. Write 1, enable BEEP ou tput, which is default value 5VSB VBAT Reserved Reserved Reserved Reserved Reserved Reserved EN_5VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Publication Release Date: Feb. 2002 - 120 - W83697HF/F Revision 0.70 ...
Page 130
... Power on Default Value 00h Attribute: Read/Write Size: 8 bits 7 6 Bit 7-0: Temperature 2 base temperature. The temperature is added by both monitor value and offset value. 9.7.42 Reserved Register -- Index 57h--58h OFFSET1<7:0> OFFSET2<7:0> Publication Release Date: Feb. 2002 - 121 - W83697HF/F Revision 0.70 ...
Page 131
... VCORE the limit range. 9.7.44 Real Time Hardware Status Register II -- Index 5Ah ( Bank 4 ) Register Location: 5Ah Power on Default Value 00h Attribute: Read Only Size: 8 bits VCORE_STS Reserved +3.3VIN_STS AVCC_STS TEMP1_STS TEMP2_STS FAN1_STS FAN2_STS Publication Release Date: Feb. 2002 - 122 - W83697HF/F Revision 0.70 ...
Page 132
... Bit 0: 5VSB Voltage Status. Set 1, the voltage of 5VSB is over the limit value. Set 0, the voltage of 5VSB is in the limit range +12VIN_STS -12VIN_STS -5VIN_STS Reserved CASE_STS Reserved Reserved Reserved 5VSB_STS VBAT_STS Reserved Reserved Reserved Reserved Reserved Reserved Publication Release Date: Feb. 2002 - 123 - W83697HF/F Revision 0.70 ...
Page 133
... Read/Write 7 PWM_CLK_SEL1 Read/Write 6-0 PRE_SCALE1[6:0] Read/Write PWM frequency = (Input Clock / Pre-scale) / 256 W83697HF/F Description Description PWM Input Clock Select. This bit select Fan 1 input clock to pre-scale divider MHz 1: 180 KHz Fan 1 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 1 transfers the input clock directly to counter ...
Page 134
... Read/Write 6-0 PRE_SCALE2[6:0] Read/Write PWM frequency = (Input Clock / Pre-scale) / 256 W83697HF/F Description FanPWM1 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 1 control mode, read this register will return smart fan duty cycle ...
Page 135
... FAN2_OB Read/Write 0 FAN1_OB Read/Write W83697HF/F Description FanPWM2 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan 2 control mode, read this register will return smart fan duty cycle. ...
Page 136
... W83697HF/F Publication Release Date: Feb. 2002 - 127 - Revision 0.70 ...
Page 137
... Fan 2 target speed register for Fan Speed Cruise mode. Bit Name Read/Write 7-0 SPD_TAR_FAN2[7:0 Read/Write ] W83697HF/F Description Reserved. VTIN1 Target Temperature. Only for Thermal Cruise Mode while CR84h bit3-2 is 01. Description Fan 1 Target Speed Control. Only for Fan Speed Cruise Mode while CR84h bit3-2 is 10. ...
Page 138
... Fan 2 PWM Stop Duty Cycle Register -- 09h ( Bank 0 ) Power on default [7:0] = 0000,0001 b Bit Name Read/Write 7-0 STOP_DC2[7:0] Read/Write W83697HF/F Description Tolerance of VTIN2 Target Temperature. Only for Thermal Cruise mode. Tolerance of VTIN1 Target Temperature. Only for Thermal Cruise mode. Description Tolerance of Fan 2 Target Speed Count. Only for Fan Speed Cruise mode ...
Page 139
... Power on default [7:0] = 0011,1100 b Bit Name Read/Write 7-0 STOP_TIME2[7:0] Read/Write W83697HF/F Description In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start- up duty cycle. Description In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan ...
Page 140
... Bit Name 7-0 STEP_DOWN_T[7:0] Read/Write The time interval, which is 0.1 second unit, to decrease PWM duty in Smart Fan Control mode. Read/Write The time interval, which is 0.1 second unit, to increase PWM duty in Smart Fan Control mode. Publication Release Date: Feb. 2002 - 131 - W83697HF/F Description Description Revision 0.70 ...
Page 141
... Plug and Play Configuration The W83697HF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83697HF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B with the exception of logical device 4 for backward compatibility) which correspond to eleven individual functions: FDC (logical device 0), PRT (logical device 1), UART1 (logical device 2), ...
Page 142
... A warm reset will not affect the configuration registers. 10.2.2 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83697HF enters the default operating mode. Before the W83697HF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed ...
Page 143
... Configuration Sequence To program W83697HF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 10.3.1 Enter the extended function mode To place the chip into the extended function mode, two successive wrtites of 0x87 must be applied to Extended Function Enable Registers(EFERs, i ...
Page 144
... MOV DX,2FH MOV AL,01H OUT DX,AL ; select logical device 1 ; MOV DX,2EH MOV AL,F0H OUT DX,AL ; select CRF0 MOV DX,2FH MOV AL,3CH OUT DX,AL ; update CRF0 with value 3CH ;------------------------------------------ ; Exit extended function mode | ;------------------------------------------ MOV DX,2EH MOV AL,AAH OUT DX,AL W83697HF/F | Publication Release Date: Feb. 2002 - 135 - Revision 0.70 ...
Page 145
... Power down = 1 No Power down Bit 3 : URBPWD = 0 Power down = 1 No Power down Bit 2 : URAPWD = 0 Power down = 1 No Power down Bit 1 : PRTPWD = 0 Power down = 1 No Power down Bit 0 : FDCPWD = 0 Power down = 1 No Power down W83697HF/F Publication Release Date: Feb. 2002 - 136 - Revision 0.70 ...
Page 146
... The Compatible PnP address select registers have default values The Compatible PnP address select registers have no default value. The corresponding power-on setting pin is DTRA# (pin 50). CR25 (Default 0x00) Bit Reserved Bit 3 : URBTRI Bit 2 : URATRI Bit 1 : PRTTRI Bit 0 : FDCTRI. W83697HF/F Publication Release Date: Feb. 2002 - 137 - Revision 0.70 ...
Page 147
... Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ Bit 0 : DSUBLGRQ = 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting IRQ = 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on selecting IRQ W83697HF/F Publication Release Date: Feb. 2002 - 138 - Revision 0.70 ...
Page 148
... Bit 1~0 : Reserved CR2A(GPIO2 ~ 5& Fresh ROM Interface Select Default 0xFF if PENROM during POR, default 0x00 otherwise) Bit 7 : (PIN 86 ~89 & 91 ~94 GPIO Fresh IF (xD7 ~ XD0) Bit 6 : (PIN GPIO Fresh IF (XA7 ~ XA0) W83697HF/F Publication Release Date: Feb. 2002 - 139 - Revision 0.70 ...
Page 149
... CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise) Bit Reserved. Bit These bits select DRQ resource for FDC. = 000 DMA0 = 001 DMA1 = 010 DMA2 = 011 DMA3 = 100 - No DMA active 111 W83697HF/F Publication Release Date: Feb. 2002 - 140 - Revision 0.70 ...
Page 150
... Enhanced 3-mode FDD CRF1 (Default 0x00) Bit Boot Floppy = 00 FDD FDD FDD FDD D Bit Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. W83697HF/F Publication Release Date: Feb. 2002 - 141 - Revision 0.70 ...
Page 151
... Bit DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A Select Regular drives and 2.88 format = 01 3-mode drive = 10 2 Meg Tape = 11 Reserved Bit 2 : Reserved. Bit 1:0 : DTYPE0, DTYPE1: Drive Type select (Refer to TABLE B). CRF5 (Default 0x00) FDD1 Selection: Same as FDD0 of CRF4. W83697HF/F Publication Release Date: Feb. 2002 - 142 - Revision 0.70 ...
Page 152
... DRVDEN1(pin 3) DRATE0 4/2/1 MB 3.5”“ 2/1 MB 5.25” 2/1.6/1 MB 3.5” (3-MODE) DRATE0 DRATE0 DRATE1 Publication Release Date: Feb. 2002 - 143 - W83697HF/F SELDEN DRIVE TYPE Revision 0.70 ...
Page 153
... Printer Mode (Default) = 000 Standard and Bi-direction (SPP) mode = 001 EPP - 1.9 and SPP mode = 101 EPP - 1.7 and SPP mode = 010 ECP mode = 011 ECP and EPP - 1.9 mode = 111 ECP and EPP - 1.7 mode. W83697HF/F Publication Release Date: Feb. 2002 - 144 - Revision 0.70 ...
Page 154
... These two registers select Serial Port 2 I/O base address [0x100:0xFF8 byte boundary. CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] : These bits select IRQ resource for Serial Port 2. W83697HF/F Publication Release Date: Feb. 2002 - 145 - Revision 0.70 ...
Page 155
... ASK-IR Inverting IRTX/SOUTB 111* ASK-IR Inverting IRTX/SOUTB & 500 KHZ clock Note: The notation is normal mode in the IR function. W83697HF/F IRTX high Demodulation into SINB/IRRX Demodulation into SINB/IRRX routed to SINB/IRRX routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Publication Release Date: Feb. 2002 ...
Page 156
... Bit Activate Game Port./GP1 = 0 Game Port/GP1 is inactive. CR60 (Default 0x02, 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) These two registers select the Game Port base address [0x100:0xFFF byte boundary. W83697HF/F Publication Release Date: Feb. 2002 - 147 - Revision 0.70 ...
Page 157
... These two registers select the MIDI Port base address [0x100:0xFFF] on 2byte boundary. CR62 (Default 0x00, 0x00 ) These two registers select the GPIO5 base address [0x100:0xFFF] on 4byte boundary. IO address : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF4 base address IO address + 3 : CRF5 base address W83697HF/F Publication Release Date: Feb. 2002 - 148 - Revision 0.70 ...
Page 158
... Bit select PLED mode = 00 Power LED pin is tri-stated Power LED pin is droved low Power LED pin is a 1Hz toggle pulse with 50 duty cycle Power LED pin is a 1/4Hz toggle pulse with 50 duty cycle. W83697HF/F Publication Release Date: Feb. 2002 - 149 - Revision 0.70 ...
Page 159
... GPIO3 is inactive Bit Activate GPIO2 GPIO2 is inactive. CR60,61(Default 0x00,0x00). These two registers select the GP2,3,4 base address(0x100:FFE bytes boundary. IO address: : CRF1 base address IO address + 1 : CRF3 base address IO address + 2 : CRF7 base address W83697HF/F Publication Release Date: Feb. 2002 - 150 - Revision 0.70 ...
Page 160
... If a port is programmed input port, then its respective bit can only be read. CRF8 (GP5 inversion register. Default 0x00 ) When set to a '1', the incoming/outgoing port value is inverted. When set to a '0', the incoming/outgoing port value is the same as in data register. W83697HF/F Publication Release Date: Feb. 2002 - 151 - Revision 0.70 ...
Page 161
... CRE6 (Default 0x00) Bit Reserved. Bit CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz divided by ( CIR Baud Rate Divisor + 1). W83697HF/F PME / Publication Release Date: Feb. 2002 - 152 - ...
Page 162
... URAPME. UART A auto power management enable disable the auto power management functions enable the auto power management functions. Bit 0 : URBPME. UART B auto power management enable disable the auto power management functions enable the auto power management functions. W83697HF/F Publication Release Date: Feb. 2002 - 153 - Revision 0.70 ...
Page 163
... The status bit is set by their source function or device and is cleared by writing a1. Writing a 0 has no effect. Bit 3 : HMIRQSTS. Hardware monitor IRQ status. Bit 2 : WDTIRQSTS. Watch dog timer IRQ status. Bit 1 : CIRIRQSTS. Consumer IR IRQ status. Bit 0 : MIDIIRQSTS. MIDI IRQ status. W83697HF/F Publication Release Date: Feb. 2002 - 154 - Revision 0.70 ...
Page 164
... UART B's IRQ. PME generation due to the GPIO IRQ function or device's IRQ. PME interrupt due to hardware monitor's IRQ. PME interrupt due to hardware monitor's IRQ. PME interrupt due to watch dog timer's IRQ. Publication Release Date: Feb. 2002 - 155 - W83697HF/F (IRQIN1EN Revision 0.70 ...
Page 165
... CIR's IRQ. PME interrupt due to MIDI's IRQ. PME interrupt due to MIDI's IRQ. PME PME output enable bit. PME will be generated. Only the IRQ status bit is set. event will be generated. - 156 - W83697HF/F PME or SMI interrupt for event. Publication Release Date: Feb. 2002 Revision 0.70 ...
Page 166
... W83697HF W83697HF 921A2B282012345 921A2B282012345 1st line: Winbond logo 2nd line: the type number: W83697HF 3th line: the tracking code 921 28201234 821: packages made in '98, week 21 A: assembly house ID; A means ASE, S means SPIL.... etc. 2: Winbond internal use revision; A means version A, B means version B ...
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... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 158 - W83697HF/F Dimension in mm Dimension in inch Min Nom Max Min Nom Max 0.25 0.35 0.45 0.010 0.014 0.018 1 2.57 2.72 2 ...