wm9708 Wolfson Microelectronics plc, wm9708 Datasheet
wm9708
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wm9708 Summary of contents
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... SNR. Additional features include line-level outputs and hardware sample rate conversion. The WM9708 is fully operable on 3. mixed 3.3/5V supplies, and is packaged in a 28-lead SSOP package. BLOCK DIAGRAM ...
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... WM9708 DESCRIPTION ....................................................................................................... 1 AC’97 FEATURES ................................................................................................. 1 BLOCK DIAGRAM ................................................................................................. 1 TABLE OF CONTENTS ......................................................................................... 2 PIN CONFIGURATION ........................................................................................... 3 ORDERING INFORMATION .................................................................................. 3 PIN DESCRIPTION ................................................................................................ 4 ABSOLUTE MAXIMUM RATINGS ......................................................................... 5 RECOMMENDED OPERATING CONDITIONS ..................................................... 5 ELECTRICAL CHARACTERISTICS ...................................................................... 6 DETAILED TIMING DIAGRAMS..................................................................................... 9 AC-LINK LOW POWER MODE ...................................................................................... 9 COLD RESET ................................................................................................................ 9 WARM RESET ............................................................................................................. 10 CLOCK SPECIFICATIONS .......................................................................................... 10 DATA SETUP AND HOLD (50PF EXTERNAL LOAD) ................................................. 11 SIGNAL RISE AND FALL TIMES ...
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... AVDD 26 MONOOUT LINEOUTR 25 LINEOUTL CAP 22 VREFOUT 21 VREF 20 AGND 19 LINEINR 18 LINEINL 17 MIC1 16 CDR 15 PACKAGE 28-lead SSOP o C (Pb-free) 28-lead SSOP o C (Pb-free, tape and reel) MOISTURE PEAK SOLDERING SENSITIVITY LEVEL TEMPERATURE o MSL1 260 C o MSL1 260 C PD, Rev 4.2, August 2009 WM9708 3 ...
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... WM9708 PIN DESCRIPTION PIN NAME 28-PIN SSOP DVDD Supply 4 XTLIN Digital input XTLOUT Digital output 5 6 SDATAOUT Digital input 7 BITCLK Digital output 8 DGND Supply 9 SDATAIN Digital output 10 SYNC Digital input 11 RESETB Digital input 12 PCBEEP Analogue input CDL Analogue input ...
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... Both supplies should be powered on and off at the same time. w DVSS -0.3V AVDD -0.3V SYMBOL TEST CONDITIONS DVDD AVDD DGND AGND DVDD, AVDD = 5V DVDD, AVDD = 5V DVDD, AVDD = 5V DVDD, AVDD = 3.3V DVDD, AVDD = 3.3V DVDD, AVDD = 3.3V WM9708 MIN MAX -0.3V +7V -0.3V +7V DVDD +0.3V AVDD +0. - max / 85% RH max ...
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... WM9708 ELECTRICAL CHARACTERISTICS Test Characteristics: AVDD = 5V, GND = 0V …………..T A DVDD = 3.3V, GND = 0V …………..T PARAMETER Digital Logic Levels (DVDD = 3.3 or 5.0V) Input LOW level Input HIGH level Output LOW Output HIGH Analogue I/O Levels (Input Signals on any inputs, Outputs on LINEOUT L, R and MONOOUT) ...
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... PD, Rev 4.2, August 2009 WM9708 UNIT dB dB Vrms Vrms dB Hz kΩ kΩ kΩ kΩ kΩ Vrms Vrms ...
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... WM9708 Test Characteristics: AVDD = 5V, GND = 0V …………..T A DVDD = 3.3V, GND = 0V …………..T PARAMETER Mixer Circuit Specifications (AVDD = 3.3V) 48kHz sampling SNR CD path A-weighted (Note 1) SNR Other paths A-weighted (Note 1) Maximum input voltage Maximum output voltage on LINEOUT THD (Note 2) ...
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... C, unless otherwise stated unless otherwise stated. A SLOT 1 SLOT 2 SYNC WRITE DON'T DATA PR4 TO 0X20 CARE t S2_PDOWN SYMBOL t S2_PDOWN t RST_LOW SYMBOL t RST_LOW t RST2_CLK WM9708 MIN TYP MAX 1.0 t RST2CLK MIN TYP MAX 1.0 162.8 PD, Rev 4.2, August 2009 UNIT μs UNIT μ ...
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... WM9708 WARM RESET BITCLK Figure 3 Warm Reset Timing SYNC active high pulse width SYNC release (or falling edge) to BITCLK startup delay CLOCK SPECIFICATIONS BITCLK Figure 4 Clock Specifications (50pF External Load) PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width ...
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... MIN TYP MAX 15.0 5.0 MIN TYP MAX 2 6 CLK 2 6 CLK 2 6 SYNC 2 6 SYNC 2 6 DIN 2 6 DIN 2 6 DOUT 2 6 DOUT PD, Rev 4.2, August 2009 WM9708 UNIT ns ns UNIT ...
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... WM9708 SYSTEM INFORMATION AC'97 DIGITAL CONTROLLER Figure 7 Revision 2.1 Compliant 2-Channel Codec w CD, LINEINL/R MIC1 PCBEEP 16 12 RESETB 11 BITCLK 7 WM9708 SYNC 10 SDATAIN 9 SDATAOUT 6 Production Data 24 LINEOUTL MONO_OUT PD, Rev 4.2, August 2009 12 ...
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... In this case, the WM9708 will process the 16-bit word along with 0 padding bits in the 2 LSB locations (to make 18-bit). At the ADC output, WM9708 will provide an 18-bit word, again with 0s in the two LSB locations (20-bit). The AC’97 controller will then ignore the 4 LSBs of the 20-bit word ...
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... WM9708 supports operation as a master codec. Fundamentally, a device identified as a master produces a BITCLK as an input. CONTROL INTERFACE A digital interface has been provided to control the WM9708 and transfer data to and from it. This serial interface is compatible with the Intel AC’97 specification. The main control interface functions are: • ...
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... Production Data AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL The WM9708 incorporates a 5-pin digital serial interface that links it to the AC’97 controller. The AC- link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input and output audio streams, as well as control Register accesses, employing a time division multiplexed (TDM) scheme. ...
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... If the Valid Frame bit this indicates that the current audio frame contains at least one time slot of valid data. The next 12-bit positions sampled by the WM9708 indicate which of the corresponding 12 time slots contain valid data. It should be noted that in URA, even when slot 1 is tagged as invalid, the request bits are still valid ...
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... BITCLK. On the immediately following falling edge of BITCLK, the WM9708 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BITCLK, AC’97 transitions SDATAOUT into the first bit position of slot 0 (Valid Frame bit) ...
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... SLOT 5: OPTIONAL MODEM LINE CODEC Audio output frame slot 5 contains the MSB justified modem DAC input data. This optional AC’97 feature is not supported in the WM9708, and if data is written to this location it is ignored. This may be determined by the AC’97 controller interrogating the WM9708 reg 28h and 3Ch. ...
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... Slot special reserved time slot containing 16-bits, which are used for AC-link protocol infrastructure. Within slot 0 the first bit is a global bit (SDATAIN slot 0, bit 15) which flags whether the WM9708 is in the Codec Ready state or not. If the Codec Ready bit this indicates that the WM9708 is not ready for normal operation. This condition is normal following the desertion of power on reset for example, while the WM9708’ ...
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... The status data port delivers 16-bit control register read data. Bit (19:4) Bit (3:0) If slot 2 is tagged invalid by the WM9708, then the entire slot will be stuffed with 0s by the WM9708. SLOT 3: PCM RECORD LEFT CHANNEL Audio input frame slot 3 is the left channel output of the WM9708’s input Mux, post-ADC. ...
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... The AC’97 controller should also drive SYNC and SDATAOUT low after programming the WM9708 to this low power, halted mode. Once the WM9708 has been instructed to halt BITCLK, a special wake up protocol must be used to bring the AC-link to the active mode since normal audio output and input frames can not be communicated in the absence of BITCLK ...
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... Support for the MSB of the volume level is not provided by the WM9708. If the MSB is written to, then the WM9708 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a 1xxxxx the WM9708 interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value written to it ...
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... The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - WM9708 defaults to the PC-beep path being muted, this path will remain muted when the device is held in reset. Therefore a separate external speaker should be provided within the PC to alert the user to power on self-test problems ...
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... Below is a summary of each bit and its function. Only the MIX, MS and LPBK bits are supported by the WM9708. The MS bit controls the Mic selector. The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-link, allowing for full system performance measurements ...
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... Figure 13 illustrates one example procedure complete Powerdown of the WM9708. From normal operation sequential writes to the Powerdown Register are performed to Powerdown the WM9708 a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4) can be executed to shut down the WM9708’s digital interface (AC-link). ...
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... The part will remain in sleep mode with all its registers holding their static values. To wake up the WM9708, the AC’97 controller will send a pulse on the sync line issuing a warm reset. This will restart the WM9708’s digital interface (resetting PR4 to 0). The WM9708 can also be woken up with a cold reset ...
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... PCM converters. Default is the 48ks/s rate. Note that only Revision 2.1 recommended rates are supported by the WM9708, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read back. ...
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... WM9708 SURROUND SOUND DSS1, DSS0 Table 14 Vendor ID Registers - Reg 74 [1:0] This allows the user to connect multiple codecs to a host controller using a single AC-link interface. The volume control register is still 02h and the rate register is 2Ch. The ID pins have no effect on this mapping. SERIAL INTERFACE REGISTER MAP The following table shows the function and address of the various control bits that are loaded through the serial interface during write operations ...
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... Production Data RECOMMENDED EXTERNAL COMPONENTS DVDD C1 DGND MIXER INPUTS AC-LINK Notes: 1. C2, C3, C12, C13 and C15 should be as close to WM9708 as possible. 2. AGND and DGND should be connected together as close to WM9708 as possible. Figure 15 External Components Diagram w 3 DVDD AVDD + C2 8 DGND AGND AGND ...
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... WM9708 RECOMMENDED EXTERNAL COMPONENTS VALUES COMPONENT SUGGESTED REFERENCE VALUE C1 10μF C2 0.1μF C3 0.1μF C4 10μ C11 470nF C12 0.1μF C13 0.1μF C14 10μF C15 0.1μF C16 10μF C17 to C19 10μF C20 and C21 22pF XT 24.576 MHz Table 16 External Component Values RECOMMENDATIONS FOR 3.3V OPERATION The device’ ...
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... B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS -C- 0.10 C SEATING PLANE MAX ----- 2.0 ----- 0.25 1.85 0.30 0.38 ----- 0.25 10.50 8.20 5.60 0. WM9708 DM007.E GAUGE Θ PLANE 0. PD, Rev 4.2, August 2009 31 ...
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... WM9708 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...