X1205V8 Intersil, X1205V8 Datasheet
X1205V8
Specifications of X1205V8
Related parts for X1205V8
X1205V8 Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved. *I2C is a Trademark of Philips. All other trademarks mentioned are the property of their respective owners. X1205 FN8097.3 ...
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... X1205V8Z* (Note) 1205 Z X1205V8I* 1205I X1205V8IZ* (Note) 1205I Z *Add “T1” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage and IRQ CC BACK pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin ...
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Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address Byte are incorrect or until 200nS after a stop ending a read or ...
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AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) A Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t ...
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Write Cycle Timing SCL SDA 8th Bit of Last Byte Power-up Timing Symbol (1) t Time from Power-up to Read PUR (1) t Time from Power-up to Write PUW Notes: (1) Delays are measured from the time V V slew ...
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DESCRIPTION (continued) The powerful Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday March 21. The alarms can be polled in the Status Register or provide a ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load- capacitance to tune oscillator frequency from +116 ppm to -37 ppm when using a 12.5 pF load crystal. For more detail information see the Application section ...
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When there is a match, an alarm flag is set. The occur- rence of an alarm can be determined by polling the AL0 and AL1 bits or by enabling the IRQ output, using it as hardware flag. The alarm enable ...
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RTCF: Real Time Clock Fail Bit-Volatile This bit is set to a “1” after a total power failure. This is a read only bit that is set by hardware (X1205 inter- nally) when the device powers up after having lost ...
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... ATR value. See Application section and Intersil’s Application Note AN154 for more information. WRITING TO THE CLOCK/CONTROL REGISTERS Changing any of the nonvolatile bits of the clock/con- trol register requires the following steps: – ...
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Write one to 8 bytes to the Clock/Control Registers with the desired clock, alarm, or control data. This sequence starts with a start bit, requires a ...
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Figure 4. Valid Data Changes on the SDA Bus SCL SDA Figure 5. Valid Start and Stop Conditions SCL SDA Figure 6. Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver DEVICE ADDRESSING Following ...
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Figure 7. Slave Address, Word Address, and Data Bytes Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and the Word Address ...
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Stop and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it’s associated ACK signal stop is issued in the middle of a data ...
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Figure 10. Random Address Read Sequence S t Signals from a the Master Address r t SDA Bus Signals from the Slave Figure 11. Sequential Read Sequence Slave Signals from Address the Master SDA Bus Signals from ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are three bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ±30ppm in increments of 10ppm ...
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... Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where Vcc may disappear intermittently for short periods of time ...
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Depending on the value of supercapacitor used, backup time can last from a few days to two weeks (with >1F). A simple silicon or Schottky barrier diode can be used in series with Vcc to charge the supercapacitor, which is ...
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Referring to Figure 13, Vtrip applies to the “Internal Vcc” node which powers the entire device. This means that if Vcc is powered down and the battery voltage at Vback is higher than the Vtrip voltage, then the entire chip ...
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Small Outline Package Family (SO PIN #1 I.D. MARK 0.010 SEATING PLANE 0.004 C 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO-8 SO-14 ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...