x24022 ETC-unknow, x24022 Datasheet

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x24022

Manufacturer Part Number
x24022
Description
Serial E2prom
Manufacturer
ETC-unknow
Datasheet

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© Xicor, 1991 Patents Pending
Preliminary Information
X24022
Pin 7 No Connect
FEATURES
FUNCTIONAL DIAGRAM
3848-1
2.7V to 5.5V Power Supply
Low Power CMOS
—Active Current Less Than 1 mA
—Standby Current Less Than 50 A
Internally Organized 256 x 8
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
Four Byte Page Write Operation
—Minimizes Total Write Time Per Byte
High Reliability
—Endurance: 100,000 Cycles Per Byte
—Data Retention: 100 Years
(5) SDA
(8) V CC
(4) V SS
(6) SCL
(3) A 2
(2) A 1
(1) A 0
SLAVE ADDRESS
START
LOGIC
+COMPARATOR
STOP
REGISTER
D OUT
ACK
R/W
Serial E
LOAD
X24022
COUNTER
ADDRESS
WORD
CONTROL
LOGIC
1
PIN
2
INC
PROM
DESCRIPTION
The X24022 is a CMOS 2048 bit serial E
nally organized 256 x 8. The X24022 features a serial
interface and software protocol allowing operation on a
simple two wire bus. Three address inputs allow up to
eight devices to share a common two wire bus.
Xicor E
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years. The X24022 is avail-
able in eight pin DIP and SOIC packages.
START CYCLE
2
PROMs are designed and tested for applica-
XDEC
CK
Characteristics subject to change without notice
H.V. GENERATION
DATA REGISTER
& CONTROL
E
TIMING
64 X 32
2
YDEC
PROM
8
256 x 8 Bit
D OUT
2
PROM, inter-
3848 FHD F01

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x24022 Summary of contents

Page 1

... Xicor E PROMs are designed and tested for applica- tions requiring extended endurance. Inherent data re- tention is greater than 100 years. The X24022 is avail- able in eight pin DIP and SOIC packages. START CYCLE CONTROL LOGIC LOAD ...

Page 2

... If actively SS CC driven, they must be driven PIN CONFIGURATION PIN NAMES Symbol DIP/SOIC X24022 SCL SDA Description A –A Address Inputs 0 2 SDA Serial Data SCL Serial Clock NC No Connect ...

Page 3

... The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers, and provide the clock for both transmit and receive operations. Therefore, the X24022 will be considered a slave in all applications. Figure 1. Data Validity SCL ...

Page 4

... X24022 will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the X24022 will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no stop condition is generated by the master, the X24022 will continue to transmit data ...

Page 5

... A A and A 1 outputs an acknowledge on the SDA line. Depending on the state of the R/W bit, the X24022 will execute a read or write operation. WRITE OPERATIONS Byte Write For a write operation, the X24022 requires a second address field. This address field is the word address, ...

Page 6

... This involves issuing the start condition followed by the slave address for a write operation. If the X24022 is still busy with the write operation no ACK will be returned. If the X24022 has completed the write operation an ACK will be returned and the master can then proceed with the next read or write operation (See Flow 1) ...

Page 7

... R/W bit set to one. This will be followed by an acknowledge from the X24022 and then by the eight bit word. The read operation is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. ...

Page 8

... At the end of the address space (address 255), the counter “rolls over” to address 0 and the X24022 continues to output data for each acknowledge received. Refer to Figure 9 for the address, acknowl- edge and data transfer sequence. ...

Page 9

... Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. Max. Supply Voltage 70 C X24022 +85 C X24022-3 +125 C X24022-2.7 3848 PGM T02 Limits Min. Max. Units ...

Page 10

... X24022 A.C. CONDITIONS OF TEST Input Pulse Levels V CC Input Rise and Fall Times Input and Output Timing Levels A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions unless otherwise specified) Read & Write Cycle Limits Symbol f SCL Clock Frequency SCL T Noise Suppression Time Constant at SCL, SDA Inputs ...

Page 11

... Write Cycle Time WR The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the X24022 Write Cycle Timing SCL SDA 8th BIT WORD n Notes: (5) Typical values are for T ...

Page 12

... X24022 NOTES 12 ...

Page 13

... X24022 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.092 (2.34) DIA. NOM. PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.325 (8.25) 0.015 (0.38) 0.300 (7.62) MAX. TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-LEAD PLASTIC SMALL OUTLINE GULL WING 0 ...

Page 14

... Temperature Range Blank = Commercial = + Industrial = – + Military = – +125 C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC X24022 X Blank = 8-Lead SOIC P = 8-Lead Plastic DIP S = 8-Lead SOIC X Blank = 4.5V to 5.5V + 4.5V to 5.5V, – + 5.5V + 5.5V, – ...

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