X5648 INTERSIL [Intersil Corporation], X5648 Datasheet

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X5648

Manufacturer Part Number
X5648
Description
CPU Supervisor with 64Kbit SPI EEPROM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
CPU Supervisor with 64Kbit SPI EEPROM
FEATURES
• Low V
• Long battery life with low power consumption
• 64Kbits of EEPROM
• Built-in inadvertent write protection
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
• 2.7V to 5.5V and 4.5V to 5.5V power supply
• Available packages
BLOCK DIAGRAM
—Five standard reset threshold voltages
—Re-program low V
—Reset signal valid to V
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
—In circuit programmable ROM mode
—32-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
operation
—14-lead SOIC, 8-lead PDIP
using special programming sequence
Block Lock
CC
detection and reset assertion
SCK
V
SO
CS
WP
CC
SI
protection
CC
®
reset threshold voltage
1
CC
= 1V
V
Data Sheet
Command
TRIP
Decode &
Register
Control
Logic
Data
+
-
1-888-INTERSIL or 1-888-352-6832
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Protect Logic
Power-on and
Low Voltage
Generation
Register
Timebase
16Kbits
16Kbits
32Kbits
Status
Reset
Reset
DESCRIPTION
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The device’s low V
user’s system from low voltage conditions by holding
RESET/RESET active when V
V
V
industry standard V
however, Intersil’s unique circuits allow the threshold to
be reprogrammed to meet custom requirements or to
fine-tune the threshold in applications requiring higher
precision.
CC
CC
returns to proper operating level and stabilizes. Five
trip point. RESET/RESET remains asserted until
March 17, 2005
All other trademarks mentioned are the property of their respective owners.
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
(Replaces X25648, X25649)
Copyright Intersil Americas Inc. 2005. All Rights Reserved
CC
TRIP
detection circuitry protects the
RESET/RESET
X5648 = RESET
X5649 = RESET
thresholds are available,
CC
X5648, X5649
falls below a minimum
FN8136.0

Related parts for X5648

X5648 Summary of contents

Page 1

... All other trademarks mentioned are the property of their respective owners. X5648, X5649 (Replaces X25648, X25649) FN8136.0 detection circuitry protects the CC falls below a minimum CC thresholds are available, TRIP RESET/RESET X5648 = RESET X5649 = RESET | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved ...

Page 2

... SCK 12 RESET/ RESET X5648, X5649 RESET/RESET SO 6 SCK Chip Select Input. CS HIGH, deselects the device and the SO output pin high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode ...

Page 3

... PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5648/X5649 activates a power-on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When V exceeds the device V ...

Page 4

... Figure 3. V Programming Sequence Flow Chart TRIP New V Applied = CC Old V Applied + Error CC Emax = Maximum Desired Error 4 X5648, X5649 V Programming TRIP Execute Reset V TRIP Sequence Set Applied = CC CC Desired V TRIP Execute Set V TRIP Sequence Apply Decrement 10mV) ...

Page 5

... WRDI/RFLB 0000 0100 RSDR 0000 0101 WRSR 0000 0001 READ 0000 0011 WRITE 0000 0010 Note: *Instructions are shown MSB in left most position. Instructions are transferred MSB first. 5 X5648, X5649 X5648/ 10K Write Enable Latch The device contains a write enable latch ...

Page 6

... This mechanism protects the block lock and watchdog bits from inadvertent corruption. In the locked state (programmable ROM Mode) the WP pin is LOW and the nonvolatile bit WPEN is “1”. This mode disables nonvolatile writes to the device’s status register. 6 X5648, X5649 Device Pin Block WP# Protected Block X Protected ...

Page 7

... Data bits 0 and 1 must be “0”. While the write is in progress following a status regis- ter or EEPROM sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. 7 X5648, X5649 ...

Page 8

... Figure 6. Read Status Register Sequence CS 0 SCK SI High Impedance SO Figure 7. Write Enable Latch Sequence CS SCK X5648, X5649 Instruction MSB High Impedance Data Out FN8136.0 March 17, 2005 ...

Page 9

... HIGH from HIGH to LOW to LOW Don’t Care: Changing: Changes State Not Allowed Known N/A Center Line is High Impedance 9 X5648, X5649 Bit Address Data Byte 3 2 ...

Page 10

... IL IH (2) This parameter is periodically sampled and not 100% tested. 10 X5648, X5649 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. ... -1.0V to +7V This is a stress rating only; the functional operation of the ...

Page 11

... CS deselect time CS (4) t Write cycle time WC Serial Input Timing CS t LEAD SCK MSB IN High Impedance SO 11 X5648, X5649 A.C. TEST CONDITIONS CC Input pulse levels 5V Input rise and fall times Input and output timing level 4.6kΩ 30pF Parameter 0 0.9 CC ...

Page 12

... CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile WC write cycle. Serial Output Timing CS SCK MSB Out ADDR SI LSB IN Power-Up and Power-Down Timing V RESET (X5648) RESET (X5649) 12 X5648, X5649 Parameter t t CYC MSB–1 Out V TRIP CC t PURST 0 Volts t PURST ...

Page 13

... RESET Output Timing Symbol V Reset trip point voltage, X5648-4.5A, X5648-4.5A TRIP Reset trip point voltage, X5648, X5649 Reset trip point voltage, X5648-2.7A, X5649-2.7A Reset trip point voltage, X5648-2.7, X5649-2 hysteresis (HIGH to LOW vs. LOW to HIGH V TH TRIP t Power-up reset time out ...

Page 14

... TRIP 25° program variation after programming (0 - 75°C). (programmed at 25°C.) tv TRIP V programming parameters are periodically sampled and are not 100% tested. TRIP 14 X5648, X5649 VP1 VPS t t VPS VPH t VPO = 1.7-5.5V ...

Page 15

... Watchdog Timer Off ( -40 25 Temp (°C) V vs. Temperature (programmed at 25°C) TRIP 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 15 X5648, X5649 PURST 205 200 = 5V) CC 195 190 185 = 5V) CC 180 175 170 165 = 3V, 5V) CC 160 90 ...

Page 16

... PACKAGING INFORMATION Half Shoulder Width On All End Pins Optional .073 (1.84) Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 16 X5648, X5649 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) Pin 1 Index Pin 1 0.300 (7.62) Ref. Seating Plane 0.150 (3.81) ...

Page 17

... NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 17 X5648, X5649 14-Lead Plastic, SOIC, Package Code S14 0.150 (3.80) 0.158 (4.00) 0.004 (0.10) 0.010 (0.25) X 45° 0.250" 0.0075 (0.19) 0.010 (0.25) FOOTPRINT 0.228 (5.80) 0.244 (6.20) ...

Page 18

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 X5648, X5649 Operating Part Number RESET Temperature Range (Active LOW) 0-70° ...

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