X9C102 INTERSIL [Intersil Corporation], X9C102 Datasheet

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X9C102

Manufacturer Part Number
X9C102
Description
Digitally Controlled Pot (XDCP)
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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Digitally Controlled Potentiometer
(XDCP™)
FEATURES
• Solid-state potentiometer
• 3-wire serial interface
• 100 wiper tap points
• 99 resistive elements
• Low power CMOS
• High reliability
• X9C102 = 1kΩ
• X9C103 = 10kΩ
• X9C503 = 50kΩ
• X9C104 = 100kΩ
• Packages
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
Device
Select
—Wiper position stored in nonvolatile memory
—Temperature compensated
—End to end resistance, ±20%
—Terminal voltages, ±5V
—V
—Active current, 3mA max.
—Standby current, 750µA max.
—Endurance, 100,000 data changes per bit
—Register data retention, 100 years
—8-lead SOIC and DIP
Increment
Up/Down
and recalled on power-up
(U/D)
CC
(INC)
(CS)
= 5V
V
CC
V
Memory
Control
(Supply Voltage)
SS
and
General
(Ground)
®
1
Data Sheet
V
R
V
H
L
W
/R
/R
/V
L
H
W
GND
U/D
INC
V
CS
CC
1-888-INTERSIL or 1-888-468-3774
Nonvolatile
Store and
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
Up/Down
Circuitry
Counter
Memory
Control
Recall
7-Bit
7-Bit
X9C102, X9C103, X9C104, X9C503
DESCRIPTION
The X9Cxxx are Intersil digitally controlled (XDCP)
potentiometers. The device consists of a resistor
array, wiper switches, a control section, and nonvola-
tile memory. The wiper position is controlled by a
three-wire interface.
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switch-
ing network. Between each element and at either end
are tap points accessible to the wiper terminal. The
position of the wiper element is controlled by the CS,
U/D, and INC inputs. The position of the wiper can be
stored in nonvolatile memory and then be recalled
upon a subsequent power-up operation.
The device can be used as a three-terminal potentiom-
eter or as a two-terminal variable resistor in a wide
variety of applications including:
– control
– parameter adjustments
– signal processing
September 19, 2005
Hundred
Decoder
One-
One
All other trademarks mentioned are the property of their respective owners.
of
Detailed
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
99
98
97
96
2
1
0
Transfer
Gates
Resistor
Array
FN8222.1
R
R
R
H
L
W
/V
/V
/V
L
H
W

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X9C102 Summary of contents

Page 1

... Select (Ground) SS General 1 X9C102, X9C103, X9C104, X9C503 September 19, 2005 DESCRIPTION The X9Cxxx are Intersil digitally controlled (XDCP) potentiometers. The device consists of a resistor array, wiper switches, a control section, and nonvola- tile memory. The wiper position is controlled by a three-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switch- ing network ...

Page 2

... RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. 2 X9C102, X9C103, X9C104, X9C503 DIP/SOIC INC 1 ...

Page 3

... CS. The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store op- eration is complete the X9C102/103/104/503 device will be placed in the low power standby mode until the device is selected once again. ...

Page 4

... Typical values are for T = 25°C and nominal supply voltage. A (5) This parameter is not 100% tested. 4 X9C102, X9C103, X9C104, X9C503 COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the ...

Page 5

... Test Point A.C. CONDITIONS OF TEST Input pulse levels Input rise and fall times 10ns Input reference levels 1.5V 5 X9C102, X9C103, X9C104, X9C503 Limits (4) Min. Typ. Max. Unit 200 750 µA ±10 µ 0.8 V ...

Page 6

... V W Notes: (6) Typical values are for T = 25°C and nominal supply voltage. A (7) This parameter is periodically sampled and not 100% tested. ( the A.C. timing diagram refers to the minimum incremental change in the V 6 X9C102, X9C103, X9C104, X9C503 Min. 100 100 2 ...

Page 7

... The high ( and low ( X9C102/103/104/503 are equivalent to the fixed termi- nals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminol- ogy and V /R references the relative position the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal ...

Page 8

... The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. 8 X9C102, X9C103, X9C104, X9C503 MODE SELECTION SYMBOL TABLE ...

Page 9

... OUT W Voltage Regulator V 317 adj (REG) = 1.25V (1 adj 2 9 X9C102, X9C103, X9C104, X9C503 Cascading Techniques + OUT (a) (b) Offset Voltage Adjustment (REG 100kΩ ...

Page 10

... PACKAGING INFORMATION Half Shoulder Width On All End Pins Optional .073 (1.84) Typ. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 10 X9C102, X9C103, X9C104, X9C503 8-Lead Plastic Dual In-Line Package Type P 0.430 (10.92) 0.360 (9.14) Pin 1 Index Pin 1 0.300 (7.62) Ref. Seating Plane 0 ...

Page 11

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 X9C102, X9C103, X9C104, X9C503 Pin 1 0.014 (0.35) 0.019 (0.49) ...

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