XC17512L XILINX [Xilinx, Inc], XC17512L Datasheet

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XC17512L

Manufacturer Part Number
XC17512L
Description
Serial Configuration PROMs
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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December 10, 1997 (Version 1.1)
Features
• On-chip address counter, incremented by each rising
• Simple interface to the FPGA; requires only one user
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
• Supports XC4000EX/XL fast configuration mode (15.0
• Low-power CMOS Floating Gate process
• Available in 5 V and 3.3 V versions
• Available in compact plastic packages: 8-pin PDIP,
• Programming support by leading programmer
• Design support using the Xilinx Alliance and
Figure 1: Simplified Block Diagram (does not show programming circuit)
December 10, 1997 (Version 1.1)
edge on the clock input
I/O pin
for compatibility with different FPGA solutions
MHz)
20-pin SOIC, and 20-pin PLCC.
manufacturers.
Foundation series software packages.
RESET/
RESET
OE or
CLK
OE/
CE
V
CC
V
PP
GND
0
0
Address Counter
5*
EPROM
Matrix
Cell
XC1701L
XC17512L
Serial Configuration PROMs
Product Specification
Description
The XC1701L, XC1701 and XC17512L serial configuration
PROMs (SCPs) provide an easy-to-use, cost-effective
method for storing Xilinx FPGA configuration bitstreams.
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCP. A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
SCP. When the FPGA is in slave mode, the SCP and the
FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
For device programming, either the Xilinx Alliance or Foun-
dation series development system compiles the FPGA
design file into a standard Hex format, which is then trans-
ferred to the programmer.
Output
TC
(3.3V),
(3.3V)
XC1701
OE
(5.0V) and
CEO
DATA
X3185
5-1

Related parts for XC17512L

XC17512L Summary of contents

Page 1

... Product Specification 0 5* Description The XC1701L, XC1701 and XC17512L serial configuration PROMs (SCPs) provide an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in master serial mode, it generates a configuration clock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin ...

Page 2

... XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs Pin Description DATA Data output, 3-stated when either are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active ...

Page 3

Controlling Serial PROMs Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. • The DATA output(s) of the of the Serial PROM(s) drives the DIN input of the lead FPGA device. • The master FPGA ...

Page 4

... XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs * If Readback is Activated, a 3.3-k Resistor is Required in Series With M1 During Configuration the 3 Pull-Down Resistor Overcomes the Internal Pull-Up, but it Allows M2 to General- be User I/O. Purpose User I/O Pins RESET Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of confi ...

Page 5

Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high imped- ance state regardless of the state of the OE input. Table 1: Truth Table for XC1700 Control Inputs Control ...

Page 6

... XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs XC1701 Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering temperature ( 1/16 in.) ...

Page 7

... XC1701L/XC17512L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum soldering temperature ( 1/16 in.) SOL Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied ...

Page 8

... XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs AC Characteristics Over Operating Condition CE RESET/OE CLK DATA Symbol Data Delay Data Delay CLK to Data Delay CAC 4 T Data Hold From CE, OE, or CLK Data Float Delay ...

Page 9

... Guaranteed by design, not tested. 4. All AC parameters are measured with V December 10, 1997 (Version 1.1) CDF Last Bit T 14 OCE XC1701 Min 2 = 0.0 V and First Bit 15 T OOE T 14 OCE X3183 XC1701L XC17512L Units Max Min Max 5-9 ...

Page 10

... XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs Ordering Information XC1701L PC20 C Device Number XC1701L XC1701 Package Type XC17512L PD8 = 8-Pin Plastic DIP SO20 = 20-Pin Plastic Small-Outline Package PC20 = 20-Pin Plastic Leaded Chip Carrier Marking Information Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package. ...

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