PESD5V0S4UF,115 NXP Semiconductors, PESD5V0S4UF,115 Datasheet - Page 8
![DIODE QUAD ESD PROTECTION 6-XSON](/photos/1/39/13915/6-xson_sot886_pkg_sml.jpg)
PESD5V0S4UF,115
Manufacturer Part Number
PESD5V0S4UF,115
Description
DIODE QUAD ESD PROTECTION 6-XSON
Manufacturer
NXP Semiconductors
Series
-r
Datasheet
1.PESD3V3S4UF115.pdf
(13 pages)
Specifications of PESD5V0S4UF,115
Package / Case
6-XSON (Micropak™), SOT-886
Voltage - Reverse Standoff (typ)
5V
Voltage - Breakdown
6.46V
Power (watts)
110W
Polarization
4 Channel Array - Unidirectional
Mounting Type
Surface Mount
Polarity
Unidirectional
Channels
4 Channels
Clamping Voltage
12 V
Operating Voltage
5 V
Breakdown Voltage
6.8 V
Peak Surge Current
10 A
Peak Pulse Power Dissipation
110 W
Capacitance
85 pF
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 65 C
Dimensions
1.05(Max) mm W x 1.5(Max) mm L
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
934061201115
PESD5V0S4UF T/R
PESD5V0S4UF T/R
PESD5V0S4UF T/R
PESD5V0S4UF T/R
NXP Semiconductors
7. Application information
PESD3V3S4UF_PESD5V0S4UF_1
Product data sheet
The PESDxS4UF is designed for the protection of up to four unidirectional data or signal
lines from the damage caused by ESD and surge pulses. The PESDxS4UF may be used
on lines where the signal polarities are either positive or negative with respect to ground.
The PESDxS4UF provides a surge capability of 110 W per line for an 8/20 s waveform
each.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the PESDxS4UF as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
Fig 9. Application diagram
ground loops.
vias.
Rev. 01 — 17 January 2008
PESD3V3S4UF; PESD5V0S4UF
unidirectional protection
1
2
3
of 4 lines
Unidirectional quadruple ESD protection diode arrays
DUT
6
5
4
n.c.
bidirectional protection
data- or transmission lines
1
2
3
of 3 lines
DUT
006aab128
6
5
4
n.c.
© NXP B.V. 2008. All rights reserved.
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