AT89S51-24PU Atmel, AT89S51-24PU Datasheet

IC MCU 4K FLASH 24MHZ 40-DIP

AT89S51-24PU

Manufacturer Part Number
AT89S51-24PU
Description
IC MCU 4K FLASH 24MHZ 40-DIP
Manufacturer
Atmel
Series
89Sr
Datasheets

Specifications of AT89S51-24PU

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
ISP/UART
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Minimum Operating Temperature
- 40 C
Controller Family/series
(8051) 8052
No. Of I/o's
32
Ram Memory Size
128Byte
Cpu Speed
24MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Features
1. Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of In-System Programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on
a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
Compatible with MCS
4K Bytes of In-System Programmable (ISP) Flash Memory
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
Green (Pb/Halide-free) Packaging Option
– Endurance: 10,000 Write/Erase Cycles
®
-51 Products
8-bit
Microcontroller
with 4K Bytes
In-System
Programmable
Flash
AT89S51
2487D–MICRO–6/08

Related parts for AT89S51-24PU

AT89S51-24PU Summary of contents

Page 1

... RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. ...

Page 2

... P1.7 3 RST 4 (RXD) P3 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 AT89S51 2 2.3 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2 ...

Page 3

... AND TIMER BLOCKS PSW INSTRUCTION REGISTER WATCH PORT 3 DOG LATCH PORT 3 DRIVERS P3.0 - P3.7 P2.0 - P2.7 PORT 2 DRIVERS PORT 2 FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DUAL DPTR PROGRAM PORT 1 ISP LOGIC LATCH PORT PORT 1 DRIVERS P1.0 - P1.7 AT89S51 3 ...

Page 4

... Port 3 Port 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter- AT89S51 4 ) because of the internal pull-ups. IL Alternate Functions MOSI (used for In-System Programming) ...

Page 5

... As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the fol- lowing table. Port Pin P3 ...

Page 6

... Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. AT89S51 6 for internal program executions during Flash programming. ...

Page 7

... Table 5-1. AT89S51 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 0D8H PSW 0D0H 00000000 0C8H 0C0H IP 0B8H XX000000 P3 0B0H 11111111 IE 0A8H 0X000000 P2 0A0H 11111111 SCON SBUF 98H 00000000 XXXXXXXX P1 90H 11111111 TCON TMOD 88H 00000000 00000000 ...

Page 8

... Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset. AT89S51 8 AUXR: Auxiliary Register Address = 8EH – ...

Page 9

... Data Memory The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space. 7. Watchdog Timer (One-time Enabled with Reset-out) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets ...

Page 10

... UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 9. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers’ operation, please click on the document link below: http://www ...

Page 11

... Interrupts The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once ...

Page 12

... XTAL1 is driven, as shown in requirements on the duty cycle of the external clock signal, since the input to the internal clock- ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Figure 11-1. Oscillator Connections Note: AT89S51 12 0 INT0 1 TF0 ...

Page 13

... SIGNAL is restored to its normal operating level and must be held active long enough to allow CC Status of External Pins During Idle and Power-down Modes Program Memory ALE Internal 1 External 1 Internal 0 External 0 AT89S51 XTAL2 XTAL1 GND PSEN PORT0 PORT1 PORT2 1 Data Data Data 1 Float Data ...

Page 14

... Program Memory Lock Bits The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 14- When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated ...

Page 15

... With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz. 16.1 Serial Programming Algorithm To program and verify the AT89S51 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: a. Apply power between VCC and GND pins. ...

Page 16

... Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase. 2. Each PROG pulse is 200 ns - 500 ns for Write Code Data. 3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. 4. RDY/BSY signal is output on P3.0 during programming don’t care. AT89S51 16 power off. CC ALE/ EA/ ...

Page 17

... XTAL1 RST GND PSEN AT89S51 ADDR. P1.0-P1.7 CC 0000H/FFFH P0 P2 A11 P2.6 P2.7 ALE SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL 2 EA 3-33 MHz XTAL1 RST GND PSEN AT89S51 V CC PGM DATA PROG RDY/ BSY PGM DATA (USE 10K PULLUPS ...

Page 18

... PROG High to BUSY Low GHBL t Byte Write Cycle Time WC Figure 18-1. Flash Programming and Verification Waveforms – Parallel Mode P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.0 (RDY/BSY) AT89S51 18 PP PROGRAMMING ADDRESS DATA DVGL GHDX t t AVGL GHAX t t SHGL ...

Page 19

... Figure 18-2. Flash Memory Serial Downloading 19. Flash Programming and Verification Waveforms – Serial Mode Figure 19-1. Serial Programming Waveforms 2487D–MICRO–6/08 AT89S51 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-33 MHz XTAL1 GND RST AT89S51 19 ...

Page 20

... For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready to be decoded. AT89S51 20 Instruction Format ...

Page 21

... SCK t SHSL = -40⋅ 85⋅ Min CLCL 8 t CLCL t CLCL 2 t CLCL 10 *NOTICE: AT89S51 t SLSH t SLIV = 4.0 - 5.5V (Unless Otherwise Noted) CC Typ Max 500 400 CLCL Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and ...

Page 22

... OL Port Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89S51 22 = -40°C to 85°C and V = 4.0V to 5.5V, unless otherwise noted Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST 1 ...

Page 23

... CLCL 252 517 585 200 300 3 t -50 CLCL 203 4 t -75 CLCL 23 t -30 CLCL 433 7 t -130 CLCL 33 t -25 CLCL 0 43 123 t -25 CLCL AT89S51 Max Units 33 MHz -65 ns CLCL -60 ns CLCL ns t -25 ns CLCL -80 ns CLCL -90 ns CLCL ns ...

Page 24

... External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 26. External Data Memory Read Cycle ALE PSEN FROM RI OR DPL PORT 0 PORT 2 AT89S51 24 t LHLL t t AVLL LLIV t LLPL t PLIV t PLAZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 t LHLL t LLDV t RLRH t LLWL ...

Page 25

... LHLL t t LLWL WLWH t LLAX t t QVWX AVLL t QVWH FROM RI OR DPL DATA OUT t AVWL P2 A15 FROM DPH t t CHCX CLCH CLCX Min AT89S51 t WHLH t WHQX FROM PCL INSTR A15 FROM PCH t CHCX t CHCL t CLCL Max Units 33 MHz ...

Page 26

... IL (1) 33. Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89S51 26 = 4.0V to 5.5V and Load Capacitance = 80 pF MHz Osc Min 1.0 ...

Page 27

... Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89S51-24AU 24 4.0V to 5.5V AT89S51-24JU AT89S51-24PU AT89S51-33AU 33 4.5V to 5.5V AT89S51-33JU AT89S51-33PU 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 2487D– ...

Page 28

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89S51 TITLE 44A, 44-lead Body Size, 1 ...

Page 29

... Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R 2487D–MICRO–6/08 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) AT89S51 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 4.191 – ...

Page 30

... PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R AT89S51 30 D PIN 0º ~ 15º REF eB TITLE 40P6, 40-lead (0.600" ...

Page 31

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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