ATTINY85-20SU Atmel, ATTINY85-20SU Datasheet - Page 36

• Manufacturer Part Number: ATTINY85-20SU
• Description: IC AVR MCU 8K 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY85-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIPATAVRBC100 - REF DESIGN KIT BATTERY CHARGER770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.1.2
7.1.3
7.2
36
Software BOD Disable
ATtiny25/45/85
ADC Noise Reduction Mode
Power-down Mode
the Analog Comparator can be powered down by setting the ACD bit in
parator Control and Status Register” on page
mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.
When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the
Watchdog to continue operating (if enabled). This sleep mode halts clk
while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out
Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change
interrupt can wake up the MCU from ADC Noise Reduction mode.
When the SM[1:0] bits are written to 10, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the Oscillator is stopped, while the external interrupts, the USI start
condition detection and the Watchdog continue operating (if enabled). Only an External Reset, a
Watchdog Reset, a Brown-out Reset, USI start condition interupt, an external level interrupt on
INT0 or a pin change interrupt can wake up the MCU. This sleep mode halts all generated
clocks, allowing operation of asynchronous modules only.
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see
152), the BOD is actively monitoring the supply voltage during a sleep period. In some devices it
is possible to save power by disabling the BOD by software in Power-Down sleep mode. The
sleep mode power consumption will then be at the same level as when BOD is globally disabled
by fuses.
If BOD is disabled by software, the BOD function is turned off immediately after entering the
sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe
operation in case the V
When the BOD has been disabled, the wake-up time from sleep mode will be the same as that
for wakeing up from RESET. The user must manually configure the wake up times such that the
bandgap reference has time to start and the BOD is working correctly before the MCU continues
executing code. See SUT[1:0] and CKSEL[3:0] fuse bits in table
BOD disable is controlled by the BODS (BOD Sleep) bit of MCU Control Register, see
– MCU Control Register” on page
writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see
MCU Control Register” on page
CC
level has dropped during the sleep period.
38.
38. Writing this bit to one turns off BOD in Power-Down, while
124. This will reduce power consumption in Idle
“Fuse Low Byte” on page 153
I/O
“ACSR – Analog Com-
, clk
Table 20-4 on page
CPU
, and clk
2586M–AVR–07/10
“MCUCR –
“MCUCR
FLASH
,