PIC16LF627A-I/SO Microchip Technology, PIC16LF627A-I/SO Datasheet - Page 110
PIC16LF627A-I/SO
Manufacturer Part Number
PIC16LF627A-I/SO
Description
IC MCU FLASH 1KX14 EEPROM 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F627A-IP.pdf
(180 pages)
2.PIC16LF627A-IP.pdf
(8 pages)
3.PIC16LF627A-ISO.pdf
(180 pages)
Specifications of PIC16LF627A-I/SO
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16LF
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC16F627A/628A/648A
14.5.1
External interrupt on the RB0/INT pin is edge triggered;
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from Sleep, if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.8 “Power-Down Mode (Sleep)” for details
on Sleep, and Figure 14-17 for timing of wake-up from
Sleep through RB0/INT interrupt.
14.5.2
An overflow (FFh
T0IF (INTCON<2>) bit. The interrupt can be enabled/
disabled by setting/clearing T0IE (INTCON<5>) bit. For
operation of the Timer0 module, see Section 6.0
“Timer0 Module”.
FIGURE 14-15:
DS40044D-page 108
Note 1:
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
PC
Instruction
Fetched
Instruction
Executed
Instruction Flow
2:
3:
4:
5:
on
(3)
RB0/INT INTERRUPT
TMR0 INTERRUPT
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 T
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
CLKOUT is available in RC and INTOSC oscillator mode.
For minimum width of INT pulse, refer to AC specs.
INTF is enabled to be set anytime during the Q4-Q1 cycles.
the
Q1
00h) in the TMR0 register will set the
Inst (PC - 1)
RB0/INT
Inst (PC)
(1)
INT PIN INTERRUPT TIMING
Q2
PC
(4)
Q3
pin,
(5)
Q4
Q1
the
Inst (PC + 1)
Inst (PC)
(1)
Q2
INTF
PC + 1
CY
Q3
. Synchronous latency = 3 T
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
operation of PORTB (Section 5.2 “PORTB and TRISB
complete description of comparator interrupts.
14.5.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/disabled
by setting/clearing the RBIE (INTCON<3>) bit. For
Registers”).
14.5.4
See
PC + 1
—
Note:
Q3
Section 10.6
Q4
(2)
CY
If a change on the I/O pin should occur
when the read operation is being executed
(starts during the Q2 cycle and ends before
the start of the Q3 cycle), then the RBIF
interrupt flag may not get set.
PORTB INTERRUPT
COMPARATOR INTERRUPT
, where T
Q1
Dummy Cycle
Inst (0004h)
Q2
0004h
CY
“Comparator
Q3
© 2005 Microchip Technology Inc.
= instruction cycle time.
Q4
Q1
Interrupts”
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
for
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