ATMEGA48A-PU Atmel, ATMEGA48A-PU Datasheet - Page 104

IC MCU AVR 4K FLASH 28PDIP

ATMEGA48A-PU

Manufacturer Part Number
ATMEGA48A-PU
Description
IC MCU AVR 4K FLASH 28PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48A-PU
Manufacturer:
Microchip Technology
Quantity:
1 051
8271C–AVR–08/10
Figure 14-7. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (see
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the compare match between OCR0x and
TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at compare
match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the
output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match.
• OCRnx changes its value from MAX, like in
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
TCNTn
OCnx
OCnx
Period
1
Figure 14-7
Table 14-7 on page
f
OCnxPCPWM
OCnx has a transition from high to low even though
2
Figure
=
----------------- -
N 510
14-7. When the OCR0A value is MAX the
f
clk_I/O
109). The actual OC0x value will only be
3
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
104

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