ATMEGA48A-PU Atmel, ATMEGA48A-PU Datasheet - Page 194

IC MCU AVR 4K FLASH 28PDIP

ATMEGA48A-PU

Manufacturer Part Number
ATMEGA48A-PU
Description
IC MCU AVR 4K FLASH 28PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48A-PU
Manufacturer:
Microchip Technology
Quantity:
1 051
19.9
8271C–AVR–08/10
Multi-processor Communication Mode
Table 19-2 on page 194
that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate
variations.
Table 19-2.
Table 19-3.
The recommendations of the maximum receiver baud rate error was made under the assump-
tion that the Receiver and Transmitter equally divides the maximum total error.
There are two possible sources for the receivers baud rate error. The Receiver’s system clock
(XTAL) will always have some minor instability over the supply voltage range and the tempera-
ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a
resonator the system clock may differ more than 2% depending of the resonators tolerance. The
second source for the error is more controllable. The baud rate generator can not always do an
exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value
that gives an acceptable low error can be used if possible.
Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering
function of incoming frames received by the USART Receiver. Frames that do not contain
address information will be ignored and not put into the receive buffer. This effectively reduces
the number of incoming frames that has to be handled by the CPU, in a system with multiple
MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
# (Data+Parity Bit)
# (Data+Parity Bit)
10
10
D
D
5
6
7
8
9
5
6
7
8
9
Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode
(U2Xn = 0)
Recommended Maximum Receiver Baud Rate Error for Double Speed Mode
(U2Xn = 1)
R
R
and
slow
slow
93.20
94.12
94.81
95.36
95.81
96.17
94.12
94.92
95.52
96.00
96.39
96.70
Table 19-3 on page 194
(%)
(%)
R
R
105.66
104.92
104,35
103.90
103.53
103.23
106.67
105.79
105.11
104.58
104.14
103.78
fast
fast
(%)
(%)
Max Total Error (%)
Max Total Error (%)
+5.66/-5.88
+4.92/-5.08
+4.35/-4.48
+3.90/-4.00
+3.53/-3.61
+3.23/-3.30
+5.79/-5.88
+5.11/-5.19
+4.58/-4.54
+4.14/-4.19
+3.78/-3.83
+6.67/-6.8
list the maximum receiver baud rate error
Recommended Max
Recommended Max
Receiver Error (%)
Receiver Error (%)
± 2.5
± 2.0
± 1.5
± 1.5
± 1.5
± 1.0
± 3.0
± 2.5
± 2.0
± 2.0
± 1.5
± 1.5
194

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