ATMEGA48A-PU Atmel, ATMEGA48A-PU Datasheet - Page 266

IC MCU AVR 4K FLASH 28PDIP

ATMEGA48A-PU

Manufacturer Part Number
ATMEGA48A-PU
Description
IC MCU AVR 4K FLASH 28PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA48A-PU
Manufacturer:
Microchip Technology
Quantity:
1 051
23.9.3
23.9.3.1
23.9.3.2
23.9.4
8271C–AVR–08/10
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
ADLAR = 0
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
• Bit 7, 5:3 – Reserved
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x7B)
Read/Write
Initial Value
262.
ADC7
ADC9
ADC1
15
15
R
R
R
R
7
0
0
7
0
0
R
7
0
ADC6
ADC8
ADC0
ACME
R/W
14
14
R
R
R
R
6
0
0
6
0
0
6
0
ADC5
ADC7
13
13
R
R
R
R
5
0
0
5
0
0
R
5
0
ADC4
ADC6
12
12
R
R
R
R
4
0
0
4
0
0
R
4
0
ADC3
ADC5
11
11
R
R
R
R
3
0
0
3
0
0
R
3
0
ADTS2
ADC4
ADC2
R/W
10
10
R
R
2
R
R
0
0
2
0
0
2
0
”ADC Conversion Result” on
ADTS1
ADC3
ADC9
ADC1
R/W
R
R
R
R
9
1
0
0
9
1
0
0
1
0
ADTS0
ADC2
ADC8
ADC0
R/W
R
R
R
R
8
0
0
0
8
0
0
0
0
0
ADCSRB
ADCH
ADCL
ADCH
ADCL
266

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