AT89LP4052-20XU Atmel, AT89LP4052-20XU Datasheet
AT89LP4052-20XU
Specifications of AT89LP4052-20XU
Related parts for AT89LP4052-20XU
AT89LP4052-20XU Summary of contents
Page 1
... CPU can deliver only 4 MIPS at the same current consump- tion. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a much lower speed and thereby greatly reduces power consumption. 8-bit Microcontroller with 2/4-Kbyte Flash AT89LP2052 AT89LP4052 3547J–MICRO–10/09 ...
Page 2
The two timer/counters in the AT89LP2052/LP4052 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition both timer/counters may ...
Page 3
Pin Description Pin Symbol Type Description I RST: External Active-High Reset input. 1 RST I VPP: Parallel Programming Voltage. Raise to 12V to enable programming. I/O P3.0: User-configurable I/O Port 3 bit 0. 2 P3.0 I RXD: Serial Port ...
Page 4
Block Diagram Single Cycle Configurable I/O Configurable I/O 5. Memory Organization The AT89LP2052/LP4052 uses a Harvard Architecture with separate address spaces for pro- gram and data memory. The program memory has a regular linear address space with support for ...
Page 5
... FFH Accessible By Indirect Addressing Only 80H 7FH Accessible By Direct and Indirect Addressing 0 AT89LP2052/LP4052 0FFF Program Memory AT89LP4052 0000 5-2). The upper 128 bytes of data memory may only FFH Accessible By Direct Addressing 80H Special Function Registers Ports Status and Control Bits Timers ...
Page 6
Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 6-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented ...
Page 7
... Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are differ- ent from those of Atmel's standard 8051 products such as AT89S52 or AT89S2051. The differences from the standard 8051 are outlined in the following paragraphs. ...
Page 8
I/O Ports The I/O ports of the AT89LP2052/LP4052 may be configured in four different modes. On the AT89LP2052/LP4052, all the I/O ports revert to input-only (tri-stated) mode at power-up or reset. In the standard 8051, all ports are weakly ...
Page 9
Figure 8-2. Register Operand Fetch Figure 8-3. Fetch Immediate Operand 3547J–MICRO–10/09 Single-cycle ALU Operation (Example: INC R0) System Clock Total Execution Time ALU Operation Execute Result Write Back Fetch Next Instruction Two-Cycle ALU Operation (Example: ADD A, System Clock Total ...
Page 10
... AT89LP2052 and 4K bytes for the AT89LP4052. This should be the responsi- bility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89LP2052 (with 2K bytes of memory), whereas LJMP 900H would not ...
Page 11
Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively inverting amplifier that can be configured for use as an on-chip oscillator, as shown in ceramic resonator may be used. For frequencies above 16MHz it is ...
Page 12
Figure 11-3. Quartz Crystal Clock Source ( Figure 11-4. Ceramic Resonator Clock Source (A) AT89LP2052/LP4052 12 Quartz Crystal Clock Input Frequency (MHz) Ceramic Resonator Clock Input ...
Page 13
Figure 11-5. Ceramic Resonator Clock Source (B) To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 11-6. External Clock Drive Configuration 3547J–MICRO–10/09 Ceramic Resonator Clock Input 7 ...
Page 14
Reset During reset, all I/O Registers are set to their initial values, the port pins are tri-stated, and the program starts execution from the Reset Vector, 0000H. The AT89LP2052/LP4052 has four sources of reset: power-on reset, brown-out reset, external ...
Page 15
Idle Mode Setting the IDL bit in PCON enters Idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The ...
Page 16
Table 13-1. – Power Control Register PCON PCON = 87H Not Bit Addressable SMOD1 SMOD0 Bit 7 6 Symbol Function SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes SMOD0 Frame ...
Page 17
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware ...
Page 18
If a request is active and conditions are met for acknowledged, a hardware subroutine call to the requested service routine will be the next instruction executed. The call itself takes four cycles. Thus, a minimum of five ...
Page 19
Table 14-2. – Interrupt Enable Register A8H Bit Addressable EA EC Bit 7 6 Symbol Function EA Global enable/disable. All interrupts are disabled when When each interrupt source is enabled/disabled by ...
Page 20
Table 14-4. – Interrupt Priority High Register IPH IPH = B7H Not Bit Addressable – PCH Bit 7 6 Symbol Function PCH Comparator Interrupt Priority High PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External ...
Page 21
A second pull-up, called the “weak” pull-up, is turned on when the port register for the pin con- tains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source current ...
Page 22
Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains a logic “0” used as a logic output, a port configured in ...
Page 23
Port Read-Modify-Write A read from a port will read either the state of the pins or the state of the port register depending on which instruction is used. Simple read instructions will always access the port pins directly. Read-modify-write ...
Page 24
Table 15-4. Port Pin P1.0 P1.1 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 16. Enhanced Timer/Counters The AT89LP2052/LP4052 has two 16-bit Timer/Counter registers: Timer 0 and Timer Timer, the register is incremented every ...
Page 25
Special Function Register TCON. GATE is in TMOD. The 13-bit register con- sists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and ...
Page 26
Mode 2 Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is the same for Timer/Counter ...
Page 27
Table 16-1. – Timer/Counter Control Register TCON TCON = 88H Bit Addressable TF1 TR1 Bit 7 6 Symbol Function TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to interrupt routine. ...
Page 28
Table 16-2. TMOD: Timer/Counter Mode Control Register TMOD = 89H Not Bit Addressable GATE C Timer1 Gate Gating control: when set Timer/Counter x is enabled only while INTx pin is high and TRx control pin is ...
Page 29
Table 16-3. – Timer/Counter Control Register B TCONB TCONB = 91H Not Bit Addressable PWM1EN PWM0EN Bit 7 6 Symbol Function PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). PWM0EN Configures Timer 0 for Pulse Width ...
Page 30
Figure 16-6. Timer/Counter 1 PWM Mode 0 Figure 16-7. Timer/Counter 1 PWM Mode 1 INT1 Pin 16.6 Timer/Counter Pin Configuration In order to use the counter input function or pulse width modulation output feature of Timer 0 or Timer 1, ...
Page 31
IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each clock cycle, an input high or low should hold ...
Page 32
An address byte differs from a data byte in that the 9th bit is “1” address byte and “0” data byte. With SM2 = 1, no slave ...
Page 33
Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation. The baud rate in Mode 2 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 ...
Page 34
Table 18-2 Table 18-2. Baud Rate Mode 0: 1 MHz Mode 2: 375K 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 18.3 More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits ...
Page 35
Figure 18-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 3547J–MICRO–10/09 INTERNAL BUS “1“ INTERNAL ...
Page 36
More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In ...
Page 37
Figure 18-2. Serial Port Mode 1 TIMER 1 OVERFLOW WRITE ÷2 TO SBUF SMOD1 SMOD1 = INTERRUPT SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET ...
Page 38
More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable ninth data bit, and a stop bit (1). On transmit, the ninth ...
Page 39
Figure 18-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3547J–MICRO–10/09 AT89LP2052/LP4052 INTERNAL BUS INTERNAL BUS 39 ...
Page 40
Figure 18-4. Serial Port Mode 3 TIMER 1 OVERFLOW WRITE TO ÷2 SBUF SMOD1 SMOD1 = INTERRUPT SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP ...
Page 41
Framing Error Detection When used for framing error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with ...
Page 42
In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 Slave 1 Slave 2 In the above example the differentiation among the 3 slaves is in the lower ...
Page 43
The interconnection between master and slave CPUs with SPI is shown in pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is ...
Page 44
Normal Mode The SPI has two modes of operation: normal (non-buffered write) and enhanced (buffered write). In normal mode, writing to the SPI data register (SPDR) of the master CPU starts the SPI clock generator and the data written ...
Page 45
Table 19-1. SPCR – SPI Control Register SPCR Address = D5H Not Bit Addressable SPIE SPE Bit 7 6 Symbol Function SPIE SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: ...
Page 46
Table 19-2. SPSR – SPI Status Register SPSR Address = AAH Not Bit Addressable SPIF WCOL Bit 7 6 Symbol Function SPIF SP interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is ...
Page 47
Figure 19-3. SPI Shift Register Diagram Serial In Transmit Byte 19.3 Serial Clock Generator The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate = baud rate) bits in SPCR control the shape and rate of SCK. ...
Page 48
Figure 19-4. SPI Transfer Format with CPHA = 0 Note: *Not defined but normally MSB of character just received Figure 19-5. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) SCK (CPOL = 0) SCK (CPOL = ...
Page 49
Analog Comparator A single analog comparator is provided on the AT89LP2052/LP4052. Comparator operation is such that the output is a logic “1” when the positive input AIN0 (P1.0) is greater than the negative input AIN1 (P1.1). Otherwise, the output ...
Page 50
Table 20-1. – Analog Comparator Control & Status Register ACSR ACSR = 97H Not Bit Addressable – – Bit 7 6 Symbol Function CIDL Comparator Idle Enable. If CIDL = 1 the comparator will continue to operate during Idle mode. ...
Page 51
Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig- gering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. The ...
Page 52
S Table 21-2. WDTCON – Watchdog Control Register WDTCON Address = A7H Not Bit Addressable PS2 PS1 Bit 7 6 Symbol Function PS2 Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog ...
Page 53
Table 22-1. Instruction Type Most arithmetic, logical, bit and transfer instructions Branches and Calls Single Byte Indirect (i.e. ADD A, @Ri, etc.) RET, RETI MOVC MUL DIV INC DPTR Table 22-2. Arithmetic Instruction ADD A, Rn ADD A, direct ADD ...
Page 54
Table 22-3. Logical Instruction CLR A CPL A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, ...
Page 55
Table 22-4. Data Transfer Instruction MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, ...
Page 56
Table 22-5. Bit Instruction SETB bit CPL C CPL bit ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Table 22-6. Branching Instruction JC rel JNC rel JB bit, rel JNB ...
Page 57
... Table 23-1. Device # AT89LP2052 AT89LP4052 The AT89LP2052/LP4052 provides two flexible interfaces for programming the Flash memory: a parallel interface which uses 10 pins; and a serial interface which uses the 4 SPI pins. The par- allel and serial programming algorithms are identical. Both interfaces support the same command format where each command is issued to the device one byte at a time ...
Page 58
... When disabling the ISP fuse during ISP, the current ISP session will remain active until RST is brought low. 4. Lock Bit Definitions: Bit 0 Lock Bit 1 Bit 1 Lock Bit 2 5. Atmel Signature Byte: AT89LP2052: Address 00H = 1EH AT89LP4052: Address 00H = 1EH 6. Symbol Key: A: Page Address Bit B: Byte Address Bit F: Fuse Bit Data L: Lock Bit Data x: Don’t Care AT89LP2052/LP4052 ...
Page 59
Status Register The current state of the memory may be accessed by reading the status register. The status reg- ister is shown in Table 23-2. Register Status – – Bit 7 6 Symbol Function Load flag. Cleared low by ...
Page 60
Figure 23-2. Flash Parallel Programming Device Connections Note: While CS is high, the interface is reset to its default state and P1 is tri-stated. CS should be brought low before the first byte of a command is issued, and should ...
Page 61
Power-up Sequence Execute the following sequence to power-up the device before parallel programming. 1. Apply power between VCC and GND pins. 2. After V 3. Wait 2 ms for the internal Power-on Reset to time out. 4. Bring P3.2 ...
Page 62
Program Enable Function: • Enables the programming interface to receive commands. • Program Enable must be the first command issued in any programming session. In parallel programming a session is active while RST remains active while ...
Page 63
Load Code Page Buffer Function: • Loads 1 page ( bytes) of data into the temporary page buffer but does not start programming. • Use for interruptible loads or loading non-contiguous bytes to a page. • The ...
Page 64
Write Code Page Function: • Programs 1 page ( bytes) of data into the Code Memory array. • Page address determined by bits [11:5] of loaded address. • The byte address (offset in page) is initialized to ...
Page 65
Read Code Page Function: • Read 1 page ( bytes) of data from the Code Memory array. • Page address determined by bits [11:5] of loaded address. • The byte address (offset in page) is initialized to ...
Page 66
Write User Signature Page Function: • Programs bytes of data into the User Signature Row. • The User Row Programming Fuse must be enabled before writing to the User Signature Row. • The byte address (offset ...
Page 67
Read User Signature Page Function: • Read bytes of data from the User Signature Row. • The byte address (offset in page) is initialized to bits [4:0] of the low address byte. The internal address is ...
Page 68
... Read Atmel Signature Page Function: • Read bytes of data from the Atmel Signature Row. • The byte address (offset in page) is initialized to bits [4:0] of the low address byte. The internal address is incremented by one on the negative edge of the XTAL1 pulse. The address will wrap around to the 1st byte of the page when incremented past 31. ...
Page 69
Write Lock Bits Function: • Program (lock) Lock Bits 1 and 2. Usage: 1. Bring CS (P3.2) low. 2. Drive P1 to AAh and pulse XTAL1 high. 3. Drive P1 to E4h and pulse XTAL1 high. 4. Drive P1 ...
Page 70
Write User Fuses Function: • Program User Fuses. • Unimplemented bits should always be written with 1s. Usage: 1. Bring CS (P3.2) low. 2. Drive P1 to AAh and pulse XTAL1 high. 3. Drive P1 to E1h and pulse ...
Page 71
Read Status Function: • Read memory status byte. Usage: 1. Bring CS (P3.2) low. 2. Drive P1 to 0xAA and pulse XTAL1 high. 3. Drive P1 to 0x60 and pulse XTAL1 high. 4. Drive P1 to 0x00 and pulse ...
Page 72
Figure 23-20. Flash Programming and Verification Waveforms in Parallel Mode AT89LP2052/LP4052 72 3547J–MICRO–10/09 ...
Page 73
Table 23-3. Symbol V PPH V PPL PWRUP t POR t CSTP t HSTL t CLXH t XTH t XTL t DSTP t DHLD t XLDO t XLDV t XLCH t CHDZ t CHBL t WRC t ...
Page 74
Figure 23-21. ISP/Serial Programming Device Connections Note: 23.5.1 Power-up Sequence Execute this sequence to power-up the device before serial programming. 1. Apply power between VCC and GND pins. 2. Keep SCK (P1.7) and SS (P1.4) at “L”. 3. Wait 10 ...
Page 75
Power-down Sequence Execute this sequence to power-down the device after serial programming. 1. Tri-state MOSI (P1.5). 2. Bring SCK (P1.7) to “L”. 3. Bring RST to “L”. 4. Bring SS (P1.4) to “L” 5. Power off Vcc. Figure 23-23. ...
Page 76
ISP Exit Sequence Execute this sequence to exit ISP and resume execution. 1. Bring SS (P1.4) to “H”. 2. Tri-state MOSI (P1.5). 3. Tri-state SCK (P1.7). 4. Bring RST to “L”. 5. Tri-state SS. Figure 23-25. In-System Programming (ISP) ...
Page 77
ISP Command Sequence The ISP multi-byte command sequence is shown in • SS should be brought low before the first byte in a command is sent and brought back high after the final byte in the command has been ...
Page 78
Figure 23-28. Serial Programming Interface Timing SS SCK MISO MOSI 24. Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +6.2V Maximum ...
Page 79
DC Characteristics T = -40°C to 85° 2.4V to 5.5V (unless otherwise noted Symbol Parameter V Input Low-voltage IL V Input Low-voltage IL1 V Input High-voltage IH V Input High-voltage IH1 V Output Low-voltage (Ports ...
Page 80
Serial Peripheral Interface Timing Table 24-1. SPI Master Characteristics Symbol Parameter t Oscillator Period CLCL t Serial Clock Cycle Time SCK t Clock High Time SHSL t Clock Low Time SLSH t Rise Time SR t Fall Time SF ...
Page 81
Figure 24-1. SPI Master Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI Figure 24-2. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-3. SPI ...
Page 82
Figure 24-4. SPI Slave Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI 24.4 External Clock Drive Figure 24-5. External Clock Drive Waveform Table 24-3. External Clock Drive Parameters Symbol Parameter 1/t Oscillator Frequency ...
Page 83
Serial Port Timing: Shift Register Mode Table 24-4. Serial Port Shift Register Timing Parameters Symbol Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock Rising Edge QVXH t Output Data Hold after Clock Rising ...
Page 84
I Test Condition, Active Mode, All Other Pins are Disconnected CC 24.6.4 I Test Condition, Idle Mode, All Other Pins are Disconnected CC 24.6.5 Clock Signal Waveform for 0.5V CC 0.45V 24.6.6 I Test Condition, Power-down ...
Page 85
... Wide, Plastic Gull Wing Small Outline (SOIC) 20X 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 3547J–MICRO–10/09 Ordering Code Package AT89LP2052-20PU AT89LP2052-20SU AT89LP2052-20XU AT89LP4052-20PU AT89LP4052-20SU AT89LP4052-20XU Package Type AT89LP2052/LP4052 Operation Range 20P3 20S2 20X Industrial (-40⋅ 85⋅ C) 20P3 20S2 ...
Page 86
Packaging Information 26.1 20P3 – PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion ...
Page 87
SOIC 3547J–MICRO–10/09 AT89LP2052/LP4052 87 ...
Page 88
TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC 0.65 (.0256) BSC 0º ~ 8º 2325 Orchard Parkway San Jose, CA 95131 R AT89LP2052/LP4052 88 PIN 1 4.50 (0.177) 4.30 (0.169) 6.60 (.260) ...
Page 89
Revision History • Revision A – March 2005 • Revision B – June 2005 • • • Revision C – August 2005 • • • • Revision D – April 2006 • Revision E – June 2006 • Revision ...
Page 90
AT89LP2052/LP4052 90 3547J–MICRO–10/09 ...
Page 91
Table of Contents 1. Description ............................................................................................... 1 2. Pin Configuration ..................................................................................... 2 3. Pin Description ......................................................................................... 3 4. Block Diagram .......................................................................................... 4 5. Memory Organization .............................................................................. 4 6. Special Function Registers ..................................................................... 6 7. Comparison to Standard 8051 ................................................................ 7 ...
Page 92
Table of Contents (Continued) 13. Power Saving Modes ............................................................................. 14 14. Interrupts ................................................................................................ 16 15. I/O Ports .................................................................................................. 20 16. Enhanced Timer/Counters .................................................................... 24 17. External Interrupts ................................................................................. 30 18. Serial Interface ....................................................................................... 31 AT89LP2052/LP4052 ii 12.3 External Reset .....................................................................................................14 ...
Page 93
Table of Contents (Continued) 19. Serial Peripheral Interface ..................................................................... 42 20. Analog Comparator ............................................................................... 49 21. Programmable Watchdog Timer ........................................................... 51 22. Instruction Set Summary ...................................................................... 52 23. Programming the Flash Memory .......................................................... 57 24. Electrical Characteristics ...................................................................... 78 25. ...
Page 94
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...