PIC18F14K50-I/SS Microchip Technology, PIC18F14K50-I/SS Datasheet - Page 120

• Manufacturer Part Number: PIC18F14K50-I/SS
• Description: IC PIC MCU FLASH 8KX16 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F14K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC244023 - PROC EXTENS PAK PIC18F1XK50DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F/LF1XK50
14.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (CCP1M<3:0>). At the same time, the inter-
rupt flag bit, CCP1IF, is set.
14.3.1
The user must configure the CCP1 pin as an output by
clearing the appropriate TRIS bit.
FIGURE 14-2:
DS41350E-page 120
I/O latch)
Note:
Compare Mode
CCP PIN CONFIGURATION
Clearing the CCP1CON register will force
the CCP1 compare output latch (depend-
ing on device configuration) to the default
low level. This is not the PORTC I/O data
latch.
0
1
T3CCP1
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR1H
TMR1H
TMR3H
Comparator
CCPR1L
TMR1L
TMR3L
Compare
Match
Preliminary
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
14.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation will not work reliably.
14.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 pin is not affected.
Only the CCP1IF interrupt flag is affected.
14.3.4
The CCP module is equipped with a Special Event Trig-
ger. This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the
(CCP1M<3:0> = 1011).
The Special Event Trigger resets the timer register pair
for whichever timer resource is currently assigned as the
module’s time base. This allows the CCPR1 registers to
serve as a programmable period register for either timer.
The Special Event Trigger can also start an A/D conver-
sion. In order to do this, the A/D converter must already
be enabled.
Special Event Trigger
CCP1CON<3:0>
Compare
Output
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
Q
 2010 Microchip Technology Inc.
Output Enable
Event
TRIS
Trigger
CCP1 pin
mode