ATMEGA48V-10MU Atmel, ATMEGA48V-10MU Datasheet - Page 241

IC AVR MCU 4K 10MHZ 1.8V 32-QFN

ATMEGA48V-10MU

Manufacturer Part Number
ATMEGA48V-10MU
Description
IC AVR MCU 4K 10MHZ 1.8V 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48V-10MU

Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Package
32MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
23
Interface Type
SPI/TWI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Processor Series
ATMEGA48x
Core
AVR8
Data Ram Size
512 B
Maximum Clock Frequency
10 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
10MHz
No. Of Timers
3
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
22.3
22.3.1
22.3.2
2545S–AVR–07/10
Register Description
ADCSRB – ADC Control and Status Register B
ACSR – Analog Comparator Control and Status Register
Table 22-1.
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-
ator. When the bandgap reference voltage is used as input to the Analog Comparator, it will take
a certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong
value. See
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
Bit
(0x7B)
Read/Write
Initial Value
Bit
0x30 (0x50)
Read/Write
Initial Value
ACME
1
1
1
1
1
1
1
“Internal Voltage Reference” on page 47
Analog Comparator Multiplexed Input (Continued)
ACD
R/W
ADEN
R
7
0
7
0
0
0
0
0
0
0
0
ACBG
ACME
R/W
R/W
“Analog Comparator Multiplexed Input” on page
6
0
6
0
MUX2..0
001
010
011
100
101
110
111
ACO
N/A
R
5
R
5
0
Analog Comparator Negative Input
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
R/W
ACI
4
0
R
4
0
ACIE
R/W
3
0
R
3
0
ADTS2
ACIC
R/W
R/W
ATmega48/88/168
2
0
2
0
ADTS1
ACIS1
R/W
R/W
1
0
1
0
240.
ADTS0
ACIS0
R/W
R/W
0
0
0
0
ADCSRB
ACSR
241

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