PIC16F627-04/SO Microchip Technology, PIC16F627-04/SO Datasheet - Page 82

• Manufacturer Part Number: PIC16F627-04/SO
• Description: IC MCU FLASH 1KX14 COMP 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627-04/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC16F62X
12.3
The USART function is similar to that on the
PIC16C74B, which includes the BRGH = 1 fix.
12.3.1
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multiprocessor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA<3>) along with the RX9 bit. The
port is now programmed so when the last bit is
received, the contents of the Receive Shift Register
(RSR) are transferred to the receive buffer. The ninth
bit of the RSR (RSR<8>) is transferred to RX9D, and
the receive interrupt is set if, and only, if RSR<8> = 1.
This feature can be used in a multiprocessor system as
follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a '1'
(instead of a '0' for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling mul-
tiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
When ADEN is enabled (='1'), all data bytes are
ignored. Following the STOP bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
TABLE 12-8:
DS40300C-page 80
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Address
USART Function
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG Baud Rate Generator Register
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
CSRC
SPEN
Bit 7
EEIF
EEIE
RX7
CMIF
CMIE
Bit 6
RX9
RX6
TX9
SREN
TXEN
RCIF
RCIE
Bit 5
RX5
CREN
SYNC
Bit 4
TXIF
TXIE
RX4
Preliminary
ADEN
Bit 3
RX3
—
—
—
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = '1'). When ADEN is
disabled (='0'), all data bytes are received and the 9th
bit can be used as the PARITY bit.
The USART Receive Block Diagram is shown in
Figure 12-8.
Reception
(RCSTA<4>).
12.3.1.1
Steps to follow when setting up an Asynchronous or
Synchronous Reception with Address Detect Enabled:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If the device has been addressed (RSR<8> = 1
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
BRGH
FERR
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH.
Enable asynchronous or synchronous commu-
nication by setting or clearing bit SYNC and
setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
Set bit RX9 to enable 9-bit reception.
Set ADEN to enable address detect.
Enable the reception by setting enable bit CREN
or SREN.
Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
If any error occurred, clear the error by clearing
enable bit CREN if it was already set.
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
Bit 2
RX2
is
OERR
TRMT
Setting up 9-bit mode with Address
Detect
Bit 1
RX1
enabled
RX9D
TX9D
Bit 0
 2003 Microchip Technology Inc.
RX0
by
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
Value on
setting
POR
bit
Value on
RESETS
all other
CREN