ATMEGA48-20MMU Atmel, ATMEGA48-20MMU Datasheet - Page 367

IC AVR MCU 4K FLASH 20MHZ 28QFN

ATMEGA48-20MMU

Manufacturer Part Number
ATMEGA48-20MMU
Description
IC AVR MCU 4K FLASH 20MHZ 28QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48-20MMU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USART/Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
28MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
35.17 Rev. 2545C-04/04
35.18 Rev. 2545B-01/04
2545S–AVR–07/10
1.
2.
3.
4.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Added section
Updated C code examples containing old IAR syntax.
Speed Grades changed: 12 MHz to 10 MHz and 24 MHz to 20 MHz
Updated
Updated
Updated
Added PDIP to “I/O and Packages”, updated “Speed Grade” and Power Consumption
Estimates in
Updated
value.
of the PRR bits to 2-wire, Timer/Counters, USART, Analog Comparator and ADC
sections.
Updated
Updated
Extra Compare Match Interrupt OCF2B added to features in section
Timer/Counter2 with PWM and Asynchronous Operation” on page 139
Updated
page 285 to 287 and
284. Fixed typo in
Updated whole
Added item 2 to 5 in
Renamed the following bits:
- SPMEN to SELFPRGEN
- PSR2 to PSRASY
- PSR10 to PSRSYNC
- Watchdog Reset to Watchdog System Reset
Updated BLBSET description in
Status Register” on page
“Speed Grades” on page
“Ordering Information” on page
“Errata ATmega88” on page
“Watchdog Timer” on page
Figure 15-2 on page 129
Table 9-1 on page
“Stack Pointer” on page 12
35.“Features” on page
“Power Reduction Register” on page 40
“Typical Characteristics” on page
Table 12-1 on page
“Errata ATmega48” on page
Table 23-1 on page
282.
38,
Table 23-5 on page
“SPMCSR – Store Program Memory Control and
and
304.
1.
48.
with RAMEND as recommended Stack Pointer
359.
66.
Table 15-3 on page
349.
248. Added note 2 to
314.
356.
258,
ATmega48/88/168
and a note regarding the use
Table 27-4
130.
Table 27-1 on page
to
Table 27-7
“8-bit
367
on

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