PIC12CE674-04/P Microchip Technology, PIC12CE674-04/P Datasheet - Page 307
PIC12CE674-04/P
Manufacturer Part Number
PIC12CE674-04/P
Description
IC MCU OTP 2KX14 A/D&EE 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(3 pages)
4.PIC12CE673-10P.pdf
(14 pages)
5.PIC12CE673-10P.pdf
(12 pages)
Specifications of PIC12CE674-04/P
Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
PIC12
No. Of I/o's
6
Eeprom Memory Size
16Byte
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE674-04/P
Manufacturer:
MIC
Quantity:
1 226
Part Number:
PIC12CE674-04/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F688T-ISL PDF datasheet
- PIC12CE673-10P PDF datasheet #2
- PIC12CE673-10P PDF datasheet #3
- PIC12CE673-10P PDF datasheet #4
- PIC12CE673-10P PDF datasheet #5
- Current page: 307 of 688
- Download datasheet (3Mb)
17.4.8
1997 Microchip Technology Inc.
Baud Rate Generator
In I
register
stops until another reload has taken place. In I
cally. If Clock Arbitration is taking place for instance, the BRG will be reloaded when the SCL pin
is sampled high
Figure 17-18: Baud Rate Generator Block Diagram
Figure 17-19: Baud Rate Generator Timing With Clock Arbitration
2
SDA
SCL
BRG
value
BRG
reload
C master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD
(Figure
SSPM3:SSPM0
17-18). When the BRG is loaded with this value, the BRG counts down to 0 and
(Figure
BRG counts
down
03h
SCL
17-19).
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
SSPM3:SSPM0
Preliminary
02h
SCL is sampled high, reload takes
place, and BRG starts its count.
BRG counts
down
Reload
Control
CLKOUT
01h
2
C master mode, the BRG is reloaded automati-
Reload
Section 17. MSSP
BRG counts
down
00h (hold off)
BRG Down Counter
DX-1
SSPADD<6:0>
SCL allowed to transition high
03h
DS31017A-page 17-31
Fosc/4
02h
17
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