PIC24F16KA102-I/SP Microchip Technology, PIC24F16KA102-I/SP Datasheet - Page 111

IC PIC MCU FLASH 16K 28-DIP

PIC24F16KA102-I/SP

Manufacturer Part Number
PIC24F16KA102-I/SP
Description
IC PIC MCU FLASH 16K 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SP

Program Memory Type
FLASH
Program Memory Size
16KB (5.5K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24F16KA102-I/SP
Manufacturer:
MICROCHIP
Quantity:
8 000
11.0
All of the device pins (except V
between the peripherals and the parallel I/O ports. All
I/O input ports feature Schmitt Trigger inputs for
improved noise immunity.
11.1
A parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1
displays how ports are shared with other peripherals
and the associated I/O pin to which they are connected.
FIGURE 11-1:
© 2009 Microchip Technology Inc.
Note:
I/O PORTS
Parallel I/O (PIO) Ports
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the I/O
Ports, refer to the “PIC24F Family Refer-
ence Manual”, Section 12. “I/O Ports with
Peripheral Pin Select (PPS)” (DS39711).
Note that the PIC24F16KA102 family
devices do not support Peripheral Pin
Select features.
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR PORT
Read LAT
Read PORT
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Peripheral Module
DD
PIO Module
and V
TRIS Latch
Data Latch
D
D
CK
CK
SS
) are shared
Q
Q
Preliminary
PIC24F16KA102 FAMILY
Output Multiplexers
1
0
1
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
may be read, but the output driver for the parallel port
bit will be disabled. If a peripheral is enabled, but the
peripheral is not actively driving a pin, that pin may be
driven by a port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the Data Latch register (LATx), read
the latch. Writes to the latch, write the latch. Reads
from the port (PORTx), read the port pins, while writes
to the port pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be
disabled. That means the corresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
0
Note:
Output Enable
Output Data
The I/O pins retain their state during Deep
Sleep. They will retain this state at
wake-up until the software restore bit
(RELEASE) is cleared.
Input Data
I/O
I/O Pin
DS39927B-page 109

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