AT89C51RC-24PU Atmel, AT89C51RC-24PU Datasheet - Page 20

IC MCU 32K FLASH 24MHZ 40-DIP

AT89C51RC-24PU

Manufacturer Part Number
AT89C51RC-24PU
Description
IC MCU 32K FLASH 24MHZ 40-DIP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51RC-24PU

Core Processor
8051
Core Size
8-Bit
Speed
24MHz
Connectivity
SPI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
24MHz
Interface Type
UART
Total Internal Ram Size
512Byte
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
32
Number Of Timers
3 bit
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant

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19. Power-down Mode
20
AT89C51RC
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down can be initiated either
by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before V
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
Figure 19-1. Oscillator Connections
Note:
Figure 19-2. External Clock Drive Configuration
Table 19-1.
Mode
Idle
Idle
Power-down
Power-down
C1, C2 = 30 pF ± 10 pF for Crystals
Status of External Pins During Idle and Power-down Modes
Program
Memory
Internal
External
Internal
External
= 40 pF ± 10 pF for Ceramic Resonators
ALE
1
1
0
0
OSCILLATOR
EXTERNAL
SIGNAL
NC
PSEN
C2
C1
1
1
0
0
PORT0
Float
Float
Data
Data
XTAL2
XTAL1
GND
XTAL2
XTAL1
GND
PORT1
Data
Data
Data
Data
Address
PORT2
CC
Data
Data
Data
is restored to its normal
PORT3
Data
Data
Data
Data
1920D–MICRO–6/08

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