PIC16F913-I/SO Microchip Technology, PIC16F913-I/SO Datasheet
PIC16F913-I/SO
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PIC16F913-I/SO Summary of contents
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... PIC16F913/914/916/917/946 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology © 2007 Microchip Technology Inc. 28/40/44/64-Pin Flash-Based, Data Sheet DS41250F ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable code protection • High-Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Low-Power Features: • Standby Current: - <100 nA @ 2.0V, typical • Operating Current μ kHz, 2.0V, typical - 220 μ ...
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... PIC16F917 8K/14K 352 PIC16F946 8K/14K 336 Note 1: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays. Pin Diagrams – PIC16F914/917, 40-Pin 40-pin PDIP RE3/MCLR/V PP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/V ...
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... Note 1: Pull-up enabled only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Timers CCP AUSART SSP — — — — — — — — — — — — ...
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... PIC16F913/914/916/917/946 Pin Diagrams – PIC16F913/916, 28-Pin 28-pin PDIP, SOIC, SSOP RE3/MCLR/V RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/V -/COM2 REF RA3/AN3/C1+/V +/COM3/SEG15 REF RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 V RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 28-pin QFN RA2/AN2/C2+/V -/COM2 REF RA3/AN3/C1+/V +/COM3/SEG15 REF RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 V SS RA7/OSC1/CLKIN/T1OSI ...
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... TABLE 2: PIC16F913/916 28-PIN (PDIP, SOIC, SSOP) SUMMARY I/O Pin A/D LCD Comparators RA0 2 AN0 SEG12 C1- RA1 3 AN1 SEG7 C2- RA2 4 AN2/V - COM2 C2+ REF RA3 5 AN3/V + SEG15/ C1+ REF COM3 RA4 6 — SEG4 C1OUT RA5 7 — SEG5 C2OUT RA6 10 — — — RA7 9 — ...
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... PIC16F913/914/916/917/946 TABLE 3: PIC16F913/916 28-PIN (QFN) SUMMARY I/O Pin A/D LCD Comparators RA0 27 AN0 SEG12 C1- RA1 28 AN1 SEG7 C2- RA2 1 AN2/V - COM2 C2+ REF RA3 2 AN3/V + SEG15/ C1+ REF COM3 RA4 3 — SEG4 C1OUT RA5 4 AN4 SEG5 C2OUT RA6 7 — — — RA7 6 — — ...
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... Pin Diagrams – PIC16F914/917, 44-Pin 44-pin TQFP RC7/RX/DT/SDI/SDA/SEG8 1 RD4/SEG17 2 RD5/SEG18 3 RD6/SEG19 4 RD7/SEG20 RB0/SEG0/INT 8 RB1/SEG1 9 RB2/SEG2 10 RB3/SEG3 11 44-pin QFN RC7/RX/DT/SDI/SDA/SEG8 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 NC 33 RC0/VLCD1 32 RA6/OSC2/CLKOUT/T1OSO 31 RA7/OSC1/CLKIN/T1OSI PIC16F914/917 RE2/AN7/SEG23 27 RE1/AN6/SEG22 26 RE0/AN5/SEG21 25 RA5/AN4/C2OUT/SS/SEG5 24 23 RA4/C1OUT/T0CKI/SEG4 1 RD4/SEG17 2 RD5/SEG18 3 RD6/SEG19 4 RD7/SEG20 5 V PIC16F914/917 ...
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... PIC16F913/914/916/917/946 TABLE 4: PIC16F914/917 44-PIN (TQFP) SUMMARY I/O Pin A/D LCD Comparators RA0 19 AN0 SEG12 C1- RA1 20 AN1 SEG7 C2- RA2 21 AN2/V - COM2 C2+ REF RA3 22 AN3/V + SEG15 C1+ REF RA4 23 — SEG4 C1OUT RA5 24 AN4 SEG5 C2OUT RA6 31 — — — RA7 30 — — — ...
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... Note 1: Pull-up enabled only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Timers CCP AUSART SSP — — — — — — — — — — — — ...
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... PIC16F913/914/916/917/946 Pin Diagram – PIC16F946 64-pin TQFP RD6/SEG19 1 RD7/SEG20 2 RG0/SEG36 3 RG1/SEG37 4 RG2/SEG38 5 RG3/SEG39 6 RG4/SEG40 7 RG5/SEG41 RF0/SEG32 11 RF1/SEG33 12 RF2/SEG34 13 RF3/SEG35 14 RB0/INT/SEG0 15 RB1/SEG1 DS41250F-page PIC16F946 RF7/SEG31 47 RF6/SEG30 46 RF5/SEG29 45 RF4/SEG28 44 RE7/SEG27 43 RE6/SEG26 RE5/SEG25 RA6/OSC2/CLKOUT/T1OSO 39 RA7/OSC1/CLKIN/T1OSI RE4/SEG24 36 RE3/MCLR RE2/AN7/SEG23 34 RE1/AN6/SEG22 RE0/AN5/SEG21 33 © 2007 Microchip Technology Inc. ...
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... SEG32 — RF1 12 — SEG33 — RF2 13 — SEG34 — Note 1: Pull-up enabled only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Timers CCP AUSART SSP — — — — — — — — — — — — ...
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... PIC16F913/914/916/917/946 TABLE 6: PIC16F946 64-PIN (TQFP) SUMMARY (CONTINUED) I/O Pin A/D LCD Comparators RF3 14 — SEG35 — RF4 45 — SEG28 — RF5 46 — SEG29 — RF6 47 — SEG30 — RF7 48 — SEG31 — RG0 3 — SEG36 — RG1 4 — SEG37 — RG2 5 — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 DS41250F-page 13 ...
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... PIC16F913/914/916/917/946 NOTES: DS41250F-page 14 © 2007 Microchip Technology Inc. ...
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... DEVICE OVERVIEW The PIC16F91X/946 devices are covered by this data sheet. They are available in 28/40/44/64-pin packages. Figure 1-1 shows a block diagram of the PIC16F913/916 device, Figure 1-2 shows a block diagram of the PIC16F914/917 device, and Figure 1-3 shows a block diagram of the PIC16F946 device. Table 1-1 shows the pinout descriptions ...
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... PIC16F913/914/916/917/946 FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM Configuration 13 Program Counter Flash 4K/ Program 8-Level Stack (13-bit) Memory Program 14 Program Memory Read Bus Instruction Reg Direct Addr 8 Power-up Instruction Oscillator Decode and Control Start-up Timer OSC1/CLKIN Power-on Timing OSC2/CLKOUT Watchdog Generation Brown-out Internal Oscillator ...
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... Timer Timing OSC2/CLKOUT Generation Brown-out Reset Internal Oscillator Block Timer0 Timer1 Comparators CCP1 CCP2 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 INT 8 Data Bus RAM 336 x 8 bytes File Registers RAM Addr 9 (PMR) Addr MUX Indirect 7 8 Addr FSR Reg STATUS Reg ...
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... RB0 INT SEG0 Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...
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... T1CKI CCP1 SEG10 Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...
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... MCLR V PP Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...
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... Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...
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... Legend Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. 2: Pins available on PIC16F914/917 and PIC16F946 only. 3: Pins available on PIC16F946 only Schmitt trigger inputs have special input levels. ...
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... PIC16F916/ 917 and PIC16F946 (0000h-1FFFh). Accessing a location above the memory boundaries for the PIC16F913 and PIC16F914 will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: ...
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... GENERAL PURPOSE REGISTER FILE The register file is organized as 256 x 8 bits in the PIC16F913/914, 352 x 8 bits in the PIC16F916/917 and 336 x 8 bits in the PIC16F946. Each register is accessed either directly or indirectly through the File Select Register (FSR) (see Section 2.5 “Indirect Addressing, INDF and FSR Registers” ...
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... Bytes 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register the PIC16F913, unimplemented data memory locations, read as ‘0’. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 File File Address Address (1) (1) 80h Indirect addr. ...
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... PIC16F913/914/916/917/946 FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC PORTD 08h TRISD PORTE 09h ...
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... Register Purpose Register 80 Bytes 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 File File Address Address (1) (1) 80h Indirect addr. 100h TMR0 101h 82h PCL 102h ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916. 3: PIC16F946 only, forced to ‘0’ on PIC16F91X. DS41250F-page 28 Bit 5 ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: PIC16F946 only, forced ‘0’ on PIC16F91X. 3: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916. 4: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.2 “Oscillator Control”. ...
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... PIC16F913/914/916/917/946 TABLE 2-3: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module Register 102h PCL Program Counter’s (PC) Least Significant Byte ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. 2: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. 3: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0CS T0SE ...
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... PIC16F913/914/916/917/946 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS ...
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... Microchip Technology Inc. PIC16F913/914/916/917/946 Note: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 6.3 “Timer1 Prescaler”. R/W-1 R/W-1 ...
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... PIC16F913/914/916/917/946 2.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 GIE ...
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... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 ...
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... PIC16F913/914/916/917/946 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register 2-5. REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 OSFIE C2IE C1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software The TMR1 register did not overflow © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... PIC16F913/914/916/917/946 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as shown in Register 2-7. REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0 R/W-0 R/W-0 OSFIF C2IF C1IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...
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... BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) Note 1: Set BOREN<1:0> the Configuration Word register for this bit to control the BOR. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 U-0 U-0 SBOREN — — ...
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... PIC16F913/914/916/917/946 2.3 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-6 shows the two situations for the loading of the PC ...
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... RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, see Figures 2-3 and 2-4. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 2-2: MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE 0 IRP Bank Select ...
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... PIC16F913/914/916/917/946 NOTES: DS41250F-page 42 © 2007 Microchip Technology Inc. ...
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... I/O PORTS The PIC16F913/914/916/917/946 family of devices includes several 8-bit PORT registers along with their corresponding TRIS registers and one four bit port: • PORTA and TRISA • PORTB and TRISB • PORTC and TRISC (1) • PORTD and TRISD • PORTE and TRISE (2) • ...
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... PIC16F913/914/916/917/946 3.2 PORTA and TRISA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register (Register 3-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i ...
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... BLOCK DIAGRAM OF RA0 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA SEG12 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Analog Input or SE12 and LCDEN SE12 and LCDEN SE12 and LCDEN To A/D Converter and Comparator V DD I/O Pin V SS ...
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... PIC16F913/914/916/917/946 3.2.1.2 RA1/AN1/C2-/SEG7 Figure 3-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • an analog input for Comparator C2 • an analog output for the LCD ...
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... BLOCK DIAGRAM OF RA2 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA COM2 To A/D Converter and Comparator To A/D Module V © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 LMUX<1:0> LCDEN and LMUX<1:0> LCDEN and LMUX<1:0> Input REF V DD I/O Pin V SS ...
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... Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA (1) COM3 To A/D Converter and Comparator To A/D Module V Note 1: PIC16F913/916 only. 2: For the PIC16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11). For the PIC16F914/917 and PIC16F946, the LCDMODE_EN = LCDEN and SE15. DS41250F-page Analog Input or LCDMODE_EN (2) LCDMODE_EN (2) ...
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... BLOCK DIAGRAM OF RA4 CM<2:0> = 110 or 101 Data Bus D WR PORTA CK Data Latch D WR TRISA CK TRIS Latch RD TRISA RD PORTA T0CKI SEG4 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 C1OUT SE4 and LCDEN SE4 and LCDEN Schmitt Trigger SE4 and LCDEN V DD I/O Pin V ...
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... PIC16F913/914/916/917/946 3.2.1.6 RA5/AN4/C2OUT/SS/SEG5 Figure 3-6 shows the diagram for this pin. The RA5 pin is configurable to function as one of the following: • a general purpose I/O • a digital output from Comparator C2 • a slave select input • an analog output for the LCD • an analog input for the ADC ...
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... CLKOUT (F Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch F = 00x, 010 OSC or T1OSCEN RD TRISA RD PORTA © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 F = 1x1 OSC From OSC1 /4) OSC 00x, 010 OSC or T1OSCEN Input Buffer Oscillator Circuit V DD I/O Pin V SS TTL ...
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... PIC16F913/914/916/917/946 3.2.1.8 RA7/OSC1/CLKIN/T1OSI Figure 3-8 shows the diagram for this pin. The RA7 pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • a clock input • a Timer1 oscillator connection FIGURE 3-8: BLOCK DIAGRAM OF RA7 To OSC2 Data Bus ...
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... RB<7:0> as inputs MOVWF TRISB ; © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.4 Additional PORTB Pin Functions RB<7:6> are used as data and clock signals, respectively, for both serial programming and the in-circuit debugger features on the device. Also, RB0 can be configured as an external interrupt input ...
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... PIC16F913/914/916/917/946 REGISTER 3-4: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x RB7 RB6 RB5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 RB<7:0>: PORTB I/O Pin bits 1 = Port pin is >V min Port pin is <V max. IL REGISTER 3-5: ...
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... Pull-up enabled 0 = Pull-up disabled Note 1: Global RBPU must be enabled for individual pull-ups to be enabled. 2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISx<7:0> = 0). © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 R/W-1 R/W-1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘0’ ...
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... PIC16F913/914/916/917/946 3.4.3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or interrupts, refer to the appropriate section in this data sheet. 3.4.3.1 RB0/INT/SEG0 Figure 3-9 shows the diagram for this pin ...
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... BLOCK DIAGRAM OF RB4 RBPU Data Bus WR PORTB WR TRISB RD TRISB RD PORTB WR IOC RD IOC Set RBIF Interrupt-on Change From other RB<7:4> pins R Write ‘0’ to RBIF COM0 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 LCDEN WPUB<4> Data Latch TRIS Latch LCDEN LCDEN LCDEN V DD ...
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... PIC16F913/914/916/917/946 3.4.3.6 RB5/COM1 Figure 3-11 shows the diagram for this pin. The RB5 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD FIGURE 3-11: BLOCK DIAGRAM OF RB5 WPUB<5> RBPU Data Bus D WR PORTB Data Latch ...
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... RD TRISB RD PORTB WR IOC RD IOC Set RBIF Interrupt-on Change From other RB<7:4> pins R Write ‘0’ to RBIF ICSPCLK SEG14 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Data Latch D Q SE14 and LCDEN CK TRIS Latch Program Mode/ICD Schmitt Trigger Program Mode or ICD Mode or (SE14 and LCDEN) ...
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... PIC16F913/914/916/917/946 3.4.3.8 RB7/ICSPDAT/ICDDAT/SEG13 Figure 3-13 shows the diagram for this pin. The RB7 pin is configurable to function as one of the following: • a general purpose I/O • an In-Circuit Serial Programming™ I/O • an ICD data I/O • an analog output for the LCD FIGURE 3-13: ...
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... Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other Resets. 2: Configuration Word register bit DEBUG <12> is also associated with PORTB. See Register 16-1 for more details. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE ...
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... PIC16F913/914/916/917/946 3.5 PORTC and TRISC Registers PORTC is an 8-bit bidirectional port. PORTC is multiplexed with several peripheral functions. PORTC pins have Schmitt Trigger input buffers. All PORTC pins have latch bits (PORTC register). They will modify the contents of the PORTC latch (when written); thus, modifying the value driven out on a pin if the corresponding TRISC bit is configured for output ...
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... CK TRIS Latch RD TRISC RD PORTC VLCD1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.5.1.3 RC2/VLCD3 Figure 3-16 shows the diagram for this pin. The RC2 pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the LCD bias voltage ≠ ...
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... PIC16F913/914/916/917/946 FIGURE 3-15: BLOCK DIAGRAM OF RC1 Data Bus PORTC Q CK Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC VLCD2 FIGURE 3-16: BLOCK DIAGRAM OF RC2 Data Bus PORTC Q CK Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC VLCD3 DS41250F-page 64 ≠ (VLCDEN and LMUX<1:0> ...
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... LCD FIGURE 3-17: BLOCK DIAGRAM OF RC3 Data Bus PORTC Q CK Data Latch TRISC Q CK TRIS Latch RD TRISC RD PORTC SEG6 and LCDEN © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 SE6 and LCDEN Schmitt Trigger SE6 and LCDEN V DD I/O Pin V SS DS41250F-page 65 ...
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... PIC16F913/914/916/917/946 3.5.1.5 RC4/T1G/SDO/SEG11 Figure 3-18 shows the diagram for this pin. The RC4pin is configurable to function as one of the following: • a general purpose I/O • a Timer1 gate input • a serial data output • an analog output for the LCD FIGURE 3-18: BLOCK DIAGRAM OF RC4 ...
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... Select) and CCPMX CCP1 Data Out Data Bus PORTC CK Q Data Latch TRISC CK Q TRIS Latch RD TRISC SE10 and LCDEN RD PORTC Timer1 Clock Input SEG10 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 0 1 Schmitt Trigger SE10 and LCDEN V DD I/O Pin V SS DS41250F-page 67 ...
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... PIC16F913/914/916/917/946 3.5.1.7 RC6/TX/CK/SCK/SCL/SEG9 Figure 3-20 shows the diagram for this pin. The RC6 pin is configurable to function as one of the following: • a general purpose I/O • an asynchronous serial output • a synchronous clock I/O • a SPI clock I/O 2 • data I/O • an analog output for the LCD ...
Page 71
... SE8 and LCDEN SEG8 Note 1: If all three data output sources are enabled, the following priority order will be used: • USART data (highest) • SSP data • PORT data (lowest) © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 0 1 SE8 and LCDEN Schmitt Trigger V DD ...
Page 72
... PIC16F913/914/916/917/946 TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 CCP1CON — — CCP1X LCDCON LCDEN SLPEN WERR LCDSE0 SE7 SE6 SE5 LCDSE1 SE15 SE14 SE13 PORTC RC7 RC6 RC5 RCSTA SPEN RX9 SREN SSPCON WCOL SSPOV SSPEN T1CON ...
Page 73
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated PORTD pin configured as an output © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 3-4: BANKSEL PORTD CLRF PORTD BANKSEL TRISD MOVLW 0FF ...
Page 74
... PIC16F913/914/916/917/946 3.6.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTD pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. ...
Page 75
... FIGURE 3-23: BLOCK DIAGRAM OF RD1 Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 LCDEN and LMUX<1:0> LCDEN and LMUX<1:0> Schmitt Trigger V DD I/O Pin V SS Schmitt Trigger V DD RD1 Pin V SS ...
Page 76
... PIC16F913/914/916/917/946 FIGURE 3-24: BLOCK DIAGRAM OF RD2 (PORT/CCP2 Select) and CCPMX CCP2 Data Out Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch RD TRISD RD PORTD CCP2 Input FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3> Data Bus PORTD CK Q Data Latch TRISD CK Q TRIS Latch ...
Page 77
... RD5 (1) TRISD TRISD7 TRISD6 TRISD5 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. Note 1: PIC16F914/917 and PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 CCP2Y CCP2M3 CCP2M2 CCP2M1 VLCDEN CS1 CS0 ...
Page 78
... TRISE<7:0>: PORTE Tri-State Control bits 1 = PORTE pin configured as an input (tri-stated PORTE pin configured as an output Note 1: PIC16F946 only. 2: PIC16F914/917 and PIC16F946 only. 3: PIC16F91X, Read as ‘0’. 4: PIC16F913/916, Read as ‘0’. DS41250F-page 76 EXAMPLE 3-5: BANKSEL PORTE CLRF PORTE BANKSEL TRISE MOVLW 0Fh MOVWF ...
Page 79
... RE5/SEG25 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.7.1.7 RE6/SEG26 Figure 3-28 shows the diagram for this pin. The RE6/SEG26 pin is configurable to function as one of the following: • ...
Page 80
... PIC16F913/914/916/917/946 FIGURE 3-26: BLOCK DIAGRAM OF RE<2:0> (PIC16F914/917 AND PIC16F946 ONLY) Data Bus PORTE CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE RD PORTE SEG<23:21> and LCDEN SEG<23:21> AN<7:5> FIGURE 3-27: BLOCK DIAGRAM OF RE3 MCLR circuit Programming mode Data Bus RD TRISE RD PORTE DS41250F-page 78 Analog Mode or SEG< ...
Page 81
... FIGURE 3-28: BLOCK DIAGRAM OF RE<7:4> (PIC16F946 ONLY) Data Bus PORTE CK Q Data Latch TRISE CK Q TRIS Latch RD TRISE RD PORTE SEG<27:24> and LCDEN SEG<27:24> AN<7:5> © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Analog Mode or SEG<27:24> and LCDEN Schmitt Trigger V DD I/O Pin V SS DS41250F-page 79 ...
Page 82
... PIC16F913/914/916/917/946 TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 ADCON0 ADFM VCFG1 VCFG0 ANSEL ANS7 ANS6 ANS5 LCDCON LCDEN SLPEN WERR (1,2) LCDSE2 SE23 SE22 SE21 (1, 3) LCDSE3 SE31 SE30 SE29 (3) (3) (3) PORTE RE7 RE6 RE5 (3) (3) TRISE ...
Page 83
... Bit is set bit 7-0 TRISF<7:0>: PORTF Tri-State Control bits 1 = PORTF pin configured as an input (tri-stated PORTF pin configured as an output Note 1: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 3-6: BANKSEL PORTF CLRF PORTF BANKSEL TRISF MOVLW 0FFh ...
Page 84
... PIC16F913/914/916/917/946 3.8.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTF pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.8.1.1 RF0/SEG32 Figure 3-29 shows the diagram for this pin. The RF0 pin is configurable to function as one of the following: • ...
Page 85
... TRISF TRISF7 TRISF6 TRISF5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF. Note 1: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 SE<35:28> and LCDEN Schmitt Trigger SE<35:28> and LCDEN Bit 4 Bit 3 Bit 2 Bit 1 VLCDEN ...
Page 86
... PIC16F913/914/916/917/946 3.9 PORTG and TRISG Registers PORTG is an 8-bit port with Schmitt Trigger input buffers. RG<5:0> are individually configured as inputs or outputs, depending on the state of the port direction. The port bits are also multiplexed with LCD segment functions. PORTG is available on the PIC16F946 only. ...
Page 87
... CK Q TRIS Latch RD TRISG RD PORTG SEG<41:36> © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 3.9.1.4 RG3/SEG39 Figure 3-30 shows the diagram for this pin. The RG3 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.5 RG4/SEG40 Figure 3-30 shows the diagram for this pin ...
Page 88
... PIC16F913/914/916/917/946 TABLE 3-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 Bit 5 LCDCON LCDEN SLPEN WERR (1) LCDSE4 SE39 SE38 SE37 (1) LCDSE5 — — — (1) PORTG — — RG5 (1) TRISG — — TRISG5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTG. ...
Page 89
... OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode. ...
Page 90
... PIC16F913/914/916/917/946 4.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 4-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...
Page 91
... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.4 External Clock Modes 4.4.1 OSCILLATOR START-UP TIMER (OST) ...
Page 92
... PIC16F913/914/916/917/946 4.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...
Page 93
... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
Page 94
... PIC16F913/914/916/917/946 4.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...
Page 95
... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 4-6) ...
Page 96
... PIC16F913/914/916/917/946 FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC ≠ 0 IRCF <2:0> System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC ≠ IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC = 0 IRCF < ...
Page 97
... OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted ...
Page 98
... PIC16F913/914/916/917/946 4.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 4-7: TWO-SPEED START-UP ...
Page 99
... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 4.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
Page 100
... PIC16F913/914/916/917/946 FIGURE 4-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...
Page 101
... T0SE, T0CS, PSA, PS<2:0> are bits in the Option register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 5.1.1 ...
Page 102
... PIC16F913/914/916/917/946 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the Option register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...
Page 103
... TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 104
... PIC16F913/914/916/917/946 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...
Page 105
... The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks ...
Page 106
... PIC16F913/914/916/917/946 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • ...
Page 107
... Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘ ...
Page 108
... PIC16F913/914/916/917/946 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 CMCON1 — — — INTCON GIE PEIE T0IE PIE1 EEIE ADIE RCIE PIR1 EEIF ADIF RCIF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L ...
Page 109
... T2CKPS<1:0> © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
Page 110
... PIC16F913/914/916/917/946 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...
Page 111
... Output synchronization to Timer1 clock input • Programmable voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 8.1 Comparator Overview A comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at V than the analog voltage at V comparator is a digital low level ...
Page 112
... PIC16F913/914/916/917/946 FIGURE 8-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM C1INV C1 Note 1: Q1 and Q3 are phases of the four-phase system clock ( held high during Sleep mode. FIGURE 8-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM C2INV C2 Note 1: Comparator output is latched on falling edge of Timer1 clock source and Q3 are phases of the four-phase system clock ( held high during Sleep mode ...
Page 113
... Analog Voltage Threshold Voltage T © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. . The analog SS and V ...
Page 114
... PIC16F913/914/916/917/946 8.2 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 8-5. I/O lines change as a function of the mode and are designated as follows: • Analog function (A): digital input buffer is disabled • ...
Page 115
... C1IN C2IN C2IN+ Legend Analog Input, ports always reads ‘0’ I/O = Normal port I/O © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Two Independent Comparators CM<2:0> = 100 A C1IN- Off (Read as ‘0’) A C1IN+ A C2IN- Off (Read as ‘0’) A C2IN+ One Independent Comparator with Reference Option CM< ...
Page 116
... PIC16F913/914/916/917/946 8.3 Comparator Control The CMCON0 register (Register 8-1) provides access to the following comparator features: • Mode selection • Output state • Output polarity • Input switch 8.3.1 COMPARATOR OUTPUT STATE Each comparator state can always be read internally via the associated CxOUT bit of the CMCON0 register. ...
Page 117
... Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 8.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 19.0 “ ...
Page 118
... PIC16F913/914/916/917/946 REGISTER 8-1: CMCON0: COMPARATOR CONFIGURATION REGISTER R-0 R-0 R/W-0 C2OUT C1OUT C2INV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C2OUT: Comparator 2 Output bit When C2INV = > < When C2INV = < > bit 6 C1OUT: Comparator 1 Output bit ...
Page 119
... Output is asynchronous Note 1: Refer to Section 6.6 “Timer1 Gate”. 2: Refer to Figure 8-3. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 8.9 Synchronizing Comparator C2 Output to Timer1 The output of Comparator C2 can be synchronized with Timer1 by setting the C2SYNC bit of the CMCON1 register. When enabled, the comparator output is latched on the falling edge of the Timer1 clock source ...
Page 120
... PIC16F913/914/916/917/946 8.10 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the com- parators. The following features are available: • Independent from Comparator operation • Two 16-level voltage ranges • Output clamped • Ratiometric with V DD The VRCON register (Register 8-3) controls the Voltage Reference module shown in Figure 8-8 ...
Page 121
... TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 VRCON VREN — VRR Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 16 Stages VREN VR<3:0> = 0000 VRR Note 1: Care should be taken to ensure V within the comparator common mode input range. ...
Page 122
... PIC16F913/914/916/917/946 NOTES: DS41250F-page 120 © 2007 Microchip Technology Inc. ...
Page 123
... SYNC 1 SPBRG BRGH x © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The AUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length Synchronous • Address detection in 9-bit mode (AUSART) • ...
Page 124
... PIC16F913/914/916/917/946 FIGURE 9-2: AUSART RECEIVE BLOCK DIAGRAM RX/DT pin Pin Buffer and Control Baud Rate Generator + 1 Multiplier SYNC SPBRG BRGH The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These registers are detailed in Register 9-1 and Register 9-2 respectively ...
Page 125
... The LCD SEG9 function must be disabled by clearing the SE9 bit of the LCDSE1 register, if the TX/CK pin is shared with the LCD peripheral. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the AUSART receiver is enabled ...
Page 126
... PIC16F913/914/916/917/946 9.1.1.4 TSR Status The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register ...
Page 127
... TRISC6 TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF VLCDEN CS1 ...
Page 128
... PIC16F913/914/916/917/946 9.1.2 AUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 9-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate ...
Page 129
... FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...
Page 130
... PIC16F913/914/916/917/946 9.1.2.8 Asynchronous Reception Set-up: 1. Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (see Section 9.2 “AUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation ...
Page 131
... SSPEN TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF VLCDEN CS1 CS0 LMUX1 ...
Page 132
... PIC16F913/914/916/917/946 REGISTER 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 CSRC TX9 TXEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode Master mode (clock generated internally from BRG) ...
Page 133
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
Page 134
... PIC16F913/914/916/917/946 9.2 AUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation. The SPBRG register determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by the BRGH bit of the TXSTA register ...
Page 135
... Microchip Technology Inc. PIC16F913/914/916/917/946 SYNC = 0, BRGH = 18.432 MHz F = 11.0592 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — — ...
Page 136
... PIC16F913/914/916/917/946 TABLE 9-5: BAUD RATES FOR ASYNCHRONOUS MODES F = 4.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 — — — 1200 1202 0.16 207 2400 2404 0.16 103 9600 9615 0.16 25 10417 10417 0.00 23 10473 19.2k 19.23k ...
Page 137
... One clock cycle is generated for each data bit. Only as many clock cycles are gener- ated as there are data bits. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.3.1.2 Synchronous Master Transmission Data is transferred out of the device on the RX/DT pin. ...
Page 138
... PIC16F913/914/916/917/946 FIGURE 9-6: SYNCHRONOUS TRANSMISSION RX/DT bit 0 bit 1 pin Word 1 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit ‘1’ TXEN bit Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. FIGURE 9-7: ...
Page 139
... RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.3.1.7 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the AUSART will shift 9-bits into the RSR for each character received ...
Page 140
... PIC16F913/914/916/917/946 FIGURE 9-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT bit 0 pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit ‘0’ CREN bit RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. ...
Page 141
... TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. The first character will immediately transfer to the TSR register and transmit ...
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... PIC16F913/914/916/917/946 9.3.2.3 AUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 9.3.1.4 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep ...
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... SLEEP instruction will be executed. If the GIE global interrupt enable bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 9.4.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • ...
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... PIC16F913/914/916/917/946 NOTES: DS41250F-page 142 © 2007 Microchip Technology Inc. ...
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... DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F913/916 devices, the module drives the panels four commons and segments. In the PIC16F914/917 devices, the module drives the panels four commons and segments ...
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... These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. 2: SEG<23:0> on PIC16F914/917, SEG<15:0> on PIC16F913/916. 3: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available when using 1/4 multiplex displays. DS41250F-page 144 SEG<41:0> LCDDATAx ...
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... Multiplex Static (COM0) 00 1/2 (COM<1:0>) 01 1/3 (COM<2:0>) 10 1/4 (COM<3:0>) 11 Note 1: On PIC16F913/916 devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 64 pixels. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-1 R/W-0 R/W-0 VLCDEN CS1 CS0 U = Unimplemented bit, read as ‘0’ ...
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... PIC16F913/914/916/917/946 REGISTER 10-2: LCDPS: LCD PRESCALER SELECT REGISTER R/W-0 R/W-0 R-0 WFT BIASMD LCDA bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary Type-A waveform (phase changes within each common interval) ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SEGx-COMy: Pixel On bits 1 = Pixel on (dark Pixel off (clear) © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R/W-0 SEn SEn SEn U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC16F913/914/916/917/946 10.2 LCD Clock Source Selection The LCD driver module has 3 possible clock sources: • F /8192 OSC • T1OSC/32 • LFINTOSC/32 The first clock source is the system clock divided by 8192 (F /8192). This divider ratio is chosen to OSC provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits LP< ...
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... COM3 Driver COM2 Driver COM1 Driver 1/4 11 Note 1: RA3 for PIC16F913/916, RD0 for PIC16F914/917 and PIC16F946 10.5 Segment Enables The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin’ ...
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... PIC16F913/914/916/917/946 FIGURE 10-3: LCD CLOCK GENERATION F ÷8192 OSC T1OSC 32 kHz ÷32 Crystal Osc. LFINTOSC ÷32 Nominal = 31 kHz CS<1:0> (LCDCON<3:2>) DS41250F-page 150 Static ÷4 1/2 ÷2 4-bit Prog Presc 1/3, 1/4 LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) © 2007 Microchip Technology Inc. ÷ Ring Counter LMUX< ...
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... FIGURE 10-4: LCD SEGMENT MAPPING WORKSHEET (SHEET © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 DS41250F-page 151 ...
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... PIC16F913/914/916/917/946 FIGURE 10-5: LCD SEGMENT MAPPING WORKSHEET (SHEET DS41250F-page 152 © 2007 Microchip Technology Inc. ...
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... TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The LCDs can be driven by two types of waveform: Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 V over a single frame, whereas Type-B waveform takes two frames ...
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... PIC16F913/914/916/917/946 FIGURE 10-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41250F-page 154 COM0 COM1 SEG0 SEG1 1 Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 10-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 SEG0 SEG1 2 Frames DS41250F-page 155 ...
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... PIC16F913/914/916/917/946 FIGURE 10-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 DS41250F-page 156 COM0 COM1 SEG0 SEG1 1 Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 10-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 SEG0 SEG1 2 Frames DS41250F-page 157 ...
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... PIC16F913/914/916/917/946 FIGURE 10-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41250F-page 158 COM0 COM1 COM2 SEG0 SEG2 SEG1 Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 10-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 COM2 SEG0 SEG1 Frames DS41250F-page 159 ...
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... PIC16F913/914/916/917/946 FIGURE 10-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41250F-page 160 COM0 COM1 COM2 SEG0 SEG2 SEG1 Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 10-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 COM2 SEG0 SEG1 Frames DS41250F-page 161 ...
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... PIC16F913/914/916/917/946 FIGURE 10-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 DS41250F-page 162 COM0 COM1 COM2 COM3 SEG0 SEG1 1 Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 10-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 COM0-SEG0 COM0-SEG1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 COM0 COM1 COM2 COM3 SEG0 SEG1 2 Frames DS41250F-page 163 ...
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... PIC16F913/914/916/917/946 10.9 LCD Interrupts The LCD timing generation provides an interrupt that defines the LCD frame timing. A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes access- ing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (T shown in Figure 10-17 ...
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... Microchip Technology Inc. PIC16F913/914/916/917/946 Table 10-5 shows the status of the LCD module during a Sleep while using each of the three available clock sources: ...
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... PIC16F913/914/916/917/946 FIGURE 10-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 COM0 COM1 COM2 SEG0 2 Frames SLEEP Instruction Execution DS41250F-page 166 Wake-up © 2007 Microchip Technology Inc ...
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... LCDCON register. 10.12 Disabling the LCD Module To disable the LCD module, write all ‘0’s to the LCDCON register. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 10.13 LCD Current Consumption When using the LCD module the current consumption consists of the following three factors: 1. ...
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... PIC16F913/914/916/917/946 TABLE 10-6: REGISTERS ASSOCIATED WITH LCD OPERATION Name Bit 7 Bit 6 Bit 5 CMCON0 C2OUT C1OUT C2INV INTCON GIE PEIE T0IE LCDCON LCDEN SLPEN WERR LCDDATA0 SEG7 SEG6 SEG5 COM0 COM0 COM0 LCDDATA1 SEG15 SEG14 SEG13 COM0 COM0 COM0 (2) LCDDATA2 SEG23 SEG22 ...
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... Shaded cells are not used by the LCD module. Note 1: These pins may be configured as port pins, depending on the oscillator mode selected. 2: PIC16F914/917 and PIC16F946 only. 3: PIC16F946 only. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 SE20 SE19 SE18 SE17 ...
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... PIC16F913/914/916/917/946 NOTES: DS41250F-page 170 © 2007 Microchip Technology Inc. ...
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... DD PLVD Trip Point LVDIF Set by Hardware © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The PLVD module includes the following capabilities: • Eight programmable trip points • Interrupt on falling V • Stable reference indication • Operation during Sleep A Block diagram of the PLVD module is shown in Figure 11-1 ...
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... PIC16F913/914/916/917/946 11.1 PLVD Operation To setup the PLVD for operation, the following steps must be taken: • Enable the module by setting the LVDEN bit of the LVDCON register. • Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register. • Wait for the reference voltage to become stable. ...
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... OSFIE C2IE C1IE PIR2 OSFIF C2IF C1IF Legend unknown unimplemented read as ‘0’. Shaded cells are not used by the PLVD module. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 U-0 R/W-1 (1) LVDEN — LVDL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC16F913/914/916/917/946 NOTES: DS41250F-page 174 © 2007 Microchip Technology Inc. ...
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... RE1/AN6 RE2/AN7 CHS Note 1: These channels are only available on PIC16F914/917 and PIC16F946 devices. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of (ADC) allows a conversion. This interrupt can be used to wake-up the device from Sleep ...
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... PIC16F913/914/916/917/946 12.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 12.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 12.1.5 “Interrupts” for more information. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V Device Frequency (F 20 MHz ...
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... PIC16F913/914/916/917/946 12.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 12-4 shows the two output formats. FIGURE 12-3: 10-BIT A/D CONVERSION RESULT FORMAT ...
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... Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 12.3 “A/D Acquisition Requirements”. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 EXAMPLE 12-1: ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ...
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... PIC16F913/914/916/917/946 REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 ADFM VCFG1 VCFG0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG1: Voltage Reference bit ...
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... RC 100 = F /4 OSC 101 = F /16 OSC 110 = F /64 OSC bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — — bit 0 ...
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... PIC16F913/914/916/917/946 REGISTER 12-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 12-4: ...
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... The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the ADC) ...
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... PIC16F913/914/916/917/946 FIGURE 12-4: ANALOG INPUT MODEL ANx Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD Note 1: See Section 19.0 “Electrical Specifications”. FIGURE 12-5: ADC TRANSFER FUNCTION 3FFh ...
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... TRISB TRISB7 TRISB6 TRISB5 TRISE TRISE7 TRISE6 TRISE5 Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE ADCS0 — — ...
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... PIC16F913/914/916/917/946 NOTES: DS41250F-page 186 © 2007 Microchip Technology Inc. ...
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... EEPROM memory and read the program memory. When code-protected, the device programmer can no longer access data or program memory. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 13.1 EEADRL and EEADRH Registers The EEADRL and EEADRH registers can address maximum of 256 bytes of data EEPROM maximum of 8K words of program Flash ...
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... PIC16F913/914/916/917/946 REGISTER 13-1: EEDATL: EEPROM/PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-0 R/W-0 R/W-0 EEDATL7 EEDATL6 EEDATL5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory ...
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... Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC16F913/914/916/917/946 13.1.2 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD control bit, and then set control bit RD of the EECON1 register. The data is available in the very next cycle, in the EEDATL register ...
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... BANKSEL EEDATL MOVF EEDATL, W MOVWF DATAL MOVF EEDATH, W MOVWF DATAH © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 on the next ; ;MS Byte of Program Address to read ;LS Byte of Program Address to read ; ;Point to PROGRAM memory ;EE Read ;Any instructions here are ignored as program ;memory is read in second cycle after BSF ...
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... PIC16F913/914/916/917/946 FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL register EERHLT TABLE 13-1: SUMMARY OF ASSOCIATED REGISTERS WITH DATA EEPROM Name Bit 7 Bit 6 Bit 5 INTCON GIE PEIE ...
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... Specifications” for information on PORTC). If read-write-modify instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<4> bit to be set, thus disabling the SDO output. © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 FIGURE 14-1: Read SDI/SDA bit 0 SDO Peripheral OE ...
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... PIC16F913/914/916/917/946 REGISTER 14-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER R/W-0 R/W-0 R-0 SMP CKE D/A bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode Input data sampled at end of data output time ...
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... Reserved 2 1110 = I C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 R/W-0 R/W-0 R/W-0 (2) (2) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
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... PIC16F913/914/916/917/946 14.2 Operation When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... Shift Register (SSPSR) LSb MSb Processor 1 © 2007 Microchip Technology Inc. PIC16F913/914/916/917/946 14.4 Typical Connection Figure 14-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
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... PIC16F913/914/916/917/946 14.5 Master Mode The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 14- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input) ...