DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 129

IC DSPIC MCU/DSP 24K 18DIP

DSPIC30F3012-30I/P

Manufacturer Part Number
DSPIC30F3012-30I/P
Description
IC DSPIC MCU/DSP 24K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F3012-30IP

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17.3
The
differentiate between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in
are used in software to determine the nature of the
Reset.
A block diagram of the On-Chip Reset Circuit is shown
in
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
FIGURE 17-2:
© 2010 Microchip Technology Inc.
Figure
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lockup (TRAPR)
Reset caused by illegal opcode or by using an
uninitialized W register as an address pointer
(IOPUWR)
MCLR
V
DD
Reset
dsPIC30F2011/2012/3012/3013
17-2.
Instruction
RESET
Trap Conflict
Illegal Opcode/
Uninitialized W Register
Brown-out
V
Sleep or Idle
Module
DD
Detect
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
BOREN
Glitch Filter
Table
Digital
POR
17-5. These bits
dsPIC30F2011/2012/3012/3013
BOR
devices
17.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally
characteristics must meet specified starting voltage
and rise rate requirements. The POR pulse will reset a
POR timer and place the device in the Reset state. The
POR also selects the device clock source identified by
the oscillator configuration fuses.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up, T
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock and the PC will
jump to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 17-3 through Figure 17-5.
DD
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
1.85V.
The
S
PWRT
R
) is applied. The T
device
Q
POR
DS70139G-page 129
+ T
supply
POR
POR
SYSRST
PWRT
) which is
, which is
. When
voltage
PWRT

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