DSPIC30F3012-30I/P Microchip Technology, DSPIC30F3012-30I/P Datasheet - Page 133

IC DSPIC MCU/DSP 24K 18DIP

DSPIC30F3012-30I/P

Manufacturer Part Number
DSPIC30F3012-30I/P
Description
IC DSPIC MCU/DSP 24K 18DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F3012-30I/P

Program Memory Type
FLASH
Program Memory Size
24KB (8K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC30F
Core
dsPIC
Maximum Clock Frequency
30 MHz
Number Of Programmable I/os
12
Data Ram Size
2 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
DSPIC30F3012-30IP

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17.4
17.4.1
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free-running timer which
runs off an on-chip RC oscillator, requiring no external
component. Therefore, the WDT timer will continue to
operate even if the main processor clock (e.g., the
crystal oscillator) fails.
17.4.2
The Watchdog Timer can be “Enabled” or “Disabled”
only through a Configuration bit (FWDTEN) in the
Configuration register, FWDT.
Setting FWDTEN = 1 enables the Watchdog Timer. The
enabling is done when programming the device. By
default, after chip erase, FWDTEN bit = 1. Any device
programmer capable of programming dsPIC30F
devices allows programming of this and other
Configuration bits.
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset
(except during Sleep). To prevent a WDT time-out, the
user must clear the Watchdog Timer using a CLRWDT
instruction.
If a WDT times out during Sleep, the device will
wake-up. The WDTO bit in the RCON register will be
cleared to indicate a wake-up resulting from a WDT
time-out.
Setting FWDTEN = 0 allows user software to
enable/disable the Watchdog Timer via the SWDTEN
(RCON<5>) control bit.
17.5
The Low-Voltage Detect (LVD) module is used to
detect when the V
threshold value, V
LVDL<3:0> bits (RCON<11:8>) and is thus user pro-
grammable. The internal voltage reference circuitry
requires a nominal amount of time to stabilize, and the
BGST bit (RCON<13>) indicates when the voltage
reference has stabilized.
In some devices, the LVD threshold voltage may be
applied externally on the LVDIN pin.
The LVD module is enabled by setting the LVDEN bit
(RCON<12>).
© 2010 Microchip Technology Inc.
Watchdog Timer (WDT)
Low-Voltage Detect
WATCHDOG TIMER OPERATION
ENABLING AND DISABLING
THE WDT
LVD
DD
, which is determined by the
of the device drops below a
dsPIC30F2011/2012/3012/3013
17.6
There are two power-saving states that can be entered
through the execution of a special instruction, PWRSAV;
these are Sleep and Idle.
The format of the PWRSAV instruction is as follows:
PWRSAV <parameter>, where ‘parameter’ defines
Idle or Sleep mode.
17.6.1
In Sleep mode, the clock to the CPU and peripherals is
shut down. If an on-chip oscillator is being used, it is
shut down.
The Fail-Safe Clock Monitor is not functional during
Sleep since there is no clock to monitor. However,
LPRC clock remains active if WDT is operational during
Sleep.
The brown-out protection circuit and the Low-Voltage
Detect circuit, if enabled, will remain functional during
Sleep.
The processor wakes up from Sleep if at least one of
the following conditions has occurred:
• any interrupt that is individually enabled and
• any Reset (POR, BOR and MCLR)
• WDT time-out
On waking up from Sleep mode, the processor will
restart the same clock that was active prior to entry into
Sleep mode. When clock switching is enabled, bits
COSC<2:0> will determine the oscillator source that
will be used on wake-up. If clock switch is disabled,
then there is only one system clock.
If the clock source is an oscillator, the clock to the
device will be held off until OST times out (indicating a
stable oscillator). If PLL is used, the system clock is
held off until LOCK = 1 (indicating that the PLL is
stable). In either case, T
are applied.
If EC, FRC, LPRC or ERC oscillators are used, then a
delay of T
delay possible on wake-up from Sleep.
Moreover, if LP oscillator was active during Sleep and
LP is the oscillator used on wake-up, then the start-up
delay will be equal to T
timer delay are not applied. In order to have the
smallest possible start-up delay when waking up from
Sleep, one of these faster wake-up options should be
selected before entering Sleep.
meets the required priority level
Note:
Power-Saving Modes
POR
SLEEP MODE
If a POR or BOR occurred, the selection of
the oscillator is based on the FOS<2:0>
and FPR<4:0> Configuration bits.
(~ 10 μs) is applied. This is the smallest
POR
POR
, T
. PWRT delay and OST
LOCK
DS70139G-page 133
and T
PWRT
delays

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