ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 187

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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19.6.4
19.6.5
19.7
19.7.1
8271C–AVR–08/10
Data Reception – The USART Receiver
Parity Generator
Disabling the Transmitter
Receiving Frames with 5 to 8 Data Bits
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART
Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt
is executed.
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed, i.e., when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxDn pin.
The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn
pin is overridden by the USART and given the function as the Receiver’s serial input. The baud
rate, mode of operation and frame format must be set up once before any serial reception can
be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer
clock.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register
until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.
When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift
Register, the contents of the Shift Register will be moved into the receive buffer. The receive
buffer can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the
Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant
bits of the data read from the UDRn will be masked to zero. The USART has to be initialized
before the function can be used.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
187

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