ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 216

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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21.2.1
21.2.2
8271C–AVR–08/10
TWI Terminology
Electrical Interconnection
The following definitions are frequently encountered in this section.
Table 21-1.
The PRTWI bit in
the 2-wire Serial Interface.
As depicted in
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Term
Master
Slave
Transmitter
Receiver
TWI Terminology
Figure
Description
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
”Minimizing Power Consumption” on page 42
21-1, both bus lines are connected to the positive supply voltage through
”Two-wire Serial Interface Characteristics” on page
must be written to zero to enable
326. Two
216

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