ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 224

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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21.6
Figure 21-10. Interfacing the Application to the TWI in a Typical Transmission
8271C–AVR–08/10
Using the TWI
writes to TWCR to
TWI bus
transmission of
1. Application
START condition sent
Status code indicates
START
initiate
2. TWINT set.
START
TWDR, and loads appropriate control
3. Check TWSR to see if START was
signals into TWCR, makin sure that
sent. Application loads SLA+W into
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a Slave.
• When a bus error has occurred due to an illegal START or STOP condition.
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 21-10
this example, a Master wishes to transmit a single data byte to a Slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired behavior is also presented.
1. The first step in a TWI transmission is to transmit a START condition. This is done by
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
and TWSTA is written to zero.
TWINT is written to one,
writing a specific value into TWCR, instructing the TWI hardware to transmit a START
condition. Which value to write is described later on. However, it is important that the
SLA+W
is a simple example of how the application can interface to the TWI hardware. In
Status code indicates
SLA+W sent, ACK
4. TWINT set.
received
A
Application loads data into TWDR, and
5. Check TWSR to see if SLA+W was
loads appropriate control signals into
TWCR, making sure that TWINT is
sent and ACK received.
written to one
Data
data sent, ACK received
Status code indicates
6. TWINT set.
A
making sure that TWINT is written to one
7. Check TWSR to see if data was sent
Application loads appropriate control
signals to send STOP into TWCR,
STOP
and ACK received.
TWINT set
Indicates
224

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