ATMEGA328P-AU Atmel, ATMEGA328P-AU Datasheet - Page 303

MCU AVR 32K FLASH 32TQFP

ATMEGA328P-AU

Manufacturer Part Number
ATMEGA328P-AU
Description
MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA328P-AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
2KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA328P-20AU
ATMEGA328P-20AU
Q3790246

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8271C–AVR–08/10
Table 27-13. Pin Name Mapping
Table 27-14. Pin Values Used to Enter Programming Mode
Table 27-15. XA1 and XA0 Coding
Table 27-16. Command Byte Bit Coding
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Signal Name in
Programming Mode
RDY/BSY
OE
WR
BS1
XA0
XA1
PAGEL
BS2
DATA
Command Byte
XA1
0
0
1
1
1000 0000
0100 0000
0010 0000
0001 0000
0001 0001
PAGEL
XA1
XA0
BS1
Pin
XA0
0
1
0
1
Action when XTAL1 is Pulsed
Load Flash or EEPROM Address (High or low address byte determined by BS1).
Load Data (High or Low data byte for Flash determined by BS1).
Load Command
No Action, Idle
Command Executed
Chip Erase
Write Fuse bits
Write Lock bits
Write Flash
Write EEPROM
{PC[1:0]: PB[5:0]}
Pin Name
Prog_enable[3]
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PC2
Symbol
I/O
I/O
O
I
I
I
I
I
I
I
Function
0: Device is busy programming, 1: Device is
ready for new command
Output Enable (Active low)
Write Pulse (Active low)
Byte Select 1 (“0” selects Low byte, “1” selects
High byte)
XTAL Action Bit 0
XTAL Action Bit 1
Program memory and EEPROM Data Page
Load
Byte Select 2 (“0” selects Low byte, “1” selects
2’nd High byte)
Bi-directional Data bus (Output when OE is low)
Value
0
0
0
0
303

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