DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 115

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

16.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger. The SSRC bits provide for up to four
alternate sources of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the
conversion trigger is under A/D clock control. The
SAMC bits select the number of A/D clocks between
the start of acquisition and the start of conversion. This
provides the fastest conversion rates on multiple
channels. SAMC must always be at least one clock
cycle.
Other trigger sources can come from timer modules or
external interrupts.
16.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling
sequencing until the next sampling trigger. The
ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority and a new
conversion will not start.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
16.6
The ADC conversion requires 14 T
the ADC conversion clock is software selected, using a
6-bit counter. There are 64 possible options for T
EQUATION 16-1:
© 2010 Microchip Technology Inc.
Programming the Start of
Conversion Trigger
Aborting a Conversion
Selecting the ADC Conversion
Clock
T
AD
= T
CY
* (0.5*(ADCS<5:0> + 1))
CLOCK
ADC CONVERSION
AD
. The source of
dsPIC30F2011/2012/3012/3013
AD
wait is
AD
.
The internal RC oscillator is selected by setting the
ADRC bit.
For correct ADC conversions, the ADC conversion
clock (T
time of 334 nsec (for V
“Electrical Characteristics”
other operating conditions.
Example 16-1
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 16-1:
Since,
Sampling Time = Acquisition Time + Conversion Time
Therefore,
Sampling Rate =
If SSRC<2:0> = ‘111’ and SAMC<4:0> = ‘00001’
Therefore,
Set ADCS<5:0> = 19
AD
ADCS<5:0> = 2
Minimum T
) must be selected to ensure a minimum T
Actual T
shows a sample calculation for the
= ~200 kHz
= 1 T
= 15 x 334 nsec
AD
T
(15 x 334 nsec)
AD
CY
AD
= 2 •
= 19.04
=
=
= 334 nsec
DD
ADC CONVERSION
CLOCK AND SAMPLING
RATE CALCULATION
= 334 nsec
= 33 .33 nsec (30 MIPS)
+ 14 T
T
33.33 nsec
= 5V). Refer to
1
T
T
CY
2
AD
33.33 nsec
CY
334 nsec
2
for minimum T
AD
(ADCS<5:0> + 1)
– 1
DS70139G-page 115
(19 + 1)
– 1
Section 20.0
AD
under
AD