DSPIC30F3013-30I/SO Microchip Technology, DSPIC30F3013-30I/SO Datasheet - Page 94

• Manufacturer Part Number: DSPIC30F3013-30I/SO
• Description: IC DSPIC MCU/DSP 24K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3013-30I/SO

• Program Memory Type: FLASH
• Program Memory Size: 24KB (8K x 24)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 10x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 30
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300018, DM330011
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301330ISO

dsPIC30F2011/2012/3012/3013
FIGURE 13-1:
Figure 13-2
between two processors. In Master mode, the clock is
generated by prescaling the system clock. Data is
transmitted as soon as a value is written to SPI1BUF.
The interrupt is generated at the middle of the transfer
of the last bit.
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the
interrupt is generated when the last bit is latched. If
SS1 control is enabled, then transmission and
reception are enabled only when SS1 = low. The SDO1
output will be disabled in SS1 mode with SS1 high.
The clock provided to the module is (F
clock is then prescaled by the primary (PPRE<1:0>)
and the secondary (SPRE<2:0>) prescale factors. The
CKE bit determines whether transmit occurs on
transition from active clock state to Idle clock state, or
vice versa. The CKP bit selects the Idle state (high or
low) for the clock.
13.1.1
A control bit, MODE16 (SPI1CON<10>), allows the
module to communicate in either 16-bit or 8-bit mode.
16-bit operation is identical to 8-bit operation except
that the number of bits transmitted is 16 instead of 8.
The user software must disable the module prior to
changing the MODE16 bit. The SPI module is reset
when the MODE16 bit is changed by the user.
A basic difference between 8-bit and 16-bit operation is
that the data is transmitted out of bit 7 of the SPI1SR
for 8-bit operation, and data is transmitted out of bit 15
of the SPI1SR for 16-bit operation. In both modes, data
is shifted into bit 0 of the SPI1SR.
DS70139G-page 94
SDO1
SCK1
SDI1
SS1
WORD AND BYTE
COMMUNICATION
depicts the a master/slave connection
SPI BLOCK DIAGRAM
SS & FSYNC
Control
Receive
SPIxBUF
Read
bit 0
SPI1SR
OSC
Control
Clock
/4). This
Clock
Shift
SPIxBUF
Write
Transmit
Data Bus
Internal
Select
Edge
13.1.2
A control bit, DISSDO, is provided to the SPI1CON
register to allow the SDO1 output to be disabled. This
will allow the SPI module to be connected in an input
only configuration. SDO1 can also be used for general
purpose I/O.
13.2
The module supports a basic framed SPI protocol in
Master or Slave mode. The control bit, FRMEN,
enables framed SPI support and causes the SS1 pin to
perform the Frame Synchronization Pulse (FSYNC)
function. The control bit, SPIFSD, determines whether
the SS1 pin is an input or an output (i.e., whether the
module
Synchronization Pulse). The frame pulse is an
active-high pulse for a single SPI clock cycle. When
Frame
transmission starts only on the subsequent transmit
edge of the SPI clock.
Framed SPI Support
Synchronization
Enable Master Clock
receives
SDO1 DISABLE
Secondary
Prescaler
1:1 – 1:8
or
© 2010 Microchip Technology Inc.
generates
is
1, 4, 16, 64
Prescaler
Primary
enabled,
the
F
the
CY
Frame
data