PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet
PIC18F2410-I/ML
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PIC18F2410-I/ML Summary of contents
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... PIC18F2410/2510/4410/4510 Rev. A1 Silicon Errata The PIC18F2410/2510/4410/4510 Rev. A1 parts you have received conform functionally to the Device Data Sheet (DS39636C), except for described below. Any Data Sheet Clarification issues related to the PIC18F2410/2510/4410/4510 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. ...
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... PIC18F2410/2510/4410/4510 2. Module: MSSP 2 After transfer is initiated, the SSPBUF register may be written for additional writes are blocked. The data transfer may be corrupted if SSPBUF is written during this time. The WCOL bit is set any time an SSPBUF write occurs during a transfer. Work around Avoid writing SSPBUF until the data transfer is complete, indicated by the setting of the SSPIF bit (PIR1< ...
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... None. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2410/2510/4410/4510 8. Module: ECCP and CCP The CCP1 and CCP2 configured for PWM mode, with 1:1 Timer2 prescaler and duty cycle set to the period minus 1, may result in the PWM output(s) remaining at a logic low level ...
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... PIC18F2410/2510/4410/4510 10. Module: ECCP When the shutdown state of the PWM pin(s) is configured to tri-state the outputs, the device may consume higher than expected current during the shutdown event. Work around Configure the PWM output for either a high or low logic state during the shutdown via the PSSAC1:PSSAC0 (ECCP1AS< ...
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... TXREG. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2410/2510/4410/4510 17. Module: Timer1/Timer3 When Timer1 or Timer3 is configured for the external clock source and the CCPxCON register is configured with 0x0B (Compare mode, trigger special event), the timer is not reset on a Special Event Trigger ...
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... PIC18F2410/2510/4410/4510 20. Module: Interrupts If an interrupt occurs during a two-cycle instruction that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register, and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register ...
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... Microchip Technology Inc. PIC18F2410/2510/4410/4510 directive instructs the compiler to not use the RETFIE FAST instruction. If the proper high priority interrupt bit is set in the IPRx register, then the interrupt is treated as high priority in spite of the pragma interruptlow directive. ...
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... Increase system clock speed to 40 MHz and adjust A/D settings accordingly. Higher system clock frequencies decrease offset error. Date Codes that pertain to this issue: All engineering and production devices. TABLE 2: A/D CONVERTER CHARACTERISTICS: PIC18F2410/2510/4410/4510 (INDUSTRIAL) Param Symbol Characteristic No. A06A E Offset Error ...
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... C slave must clear the SSPOV bit after each event to maintain normal operation. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2410/2510/4410/4510 28. Module: MSSP Master mode, the BRG value of ‘0’ may not work correctly. Work around Use a BRG value greater than ‘ ...
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... PIC18F2410/2510/4410/4510 31. Module: MSSP In SPI mode, the Buffer Full flag (BF bit in the SSPSTAT register), the Write Collision Detect bit (WCOL bit in SSPCON1) and the Receive Overflow Indicator bit (SSPOV in SSPCON1) are not reset upon disabling the SPI module (by clearing the SSPEN bit in the SSPCON1 register). ...
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... TXREG when the timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2410/2510/4410/4510 34. Module: EUSART In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON< ...
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... PIC18F2410/2510/4410/4510 37. Module: Timer1 In 16-Bit Asynchronous Counter mode (with or without use of the Timer1 oscillator), the TMR1H and TMR3H buffers do not update when TMRxL is read. This issue only affects reading the TMRxH regis- ters. The timers increments and set the interrupt flags as expected. The timer registers can also be written as expected ...
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... Q4 cycle). Work around None Date Codes that pertain to this issue: All engineering and production devices. © 2007 Microchip Technology Inc. PIC18F2410/2510/4410/4510 43. Module: 10-Bit Analog-to-Digital (A/D) Converter When the A/D clock source is selected (when ADCS2:ADCS0 = 000 or x11), in extremely rare cases, the E ...
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... PIC18F2410/2510/4410/4510 REVISION HISTORY Rev A Document (06/2006) First revision of this document. Issues 1-4 (MSSP), 5-7 (ECCP), 8 (ECCP and CCP), 9-14 (ECCP), 15-16 (EUSART), 17-19 (Timer1/ Timer3), 20 (Interrupts), 21 (A/D), 22 (BOR), 23-26 (EUSART), 27-31 (MSSP), 32 (MSSP – SPI Mode), 33- 36 (EUSART), 37 (Timer1), 38-41 (MSSP) and 42 (Reset) ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...